EEPROM array with narrow margin of voltage thresholds after erase

A nonvolatile memory having at least one reference potential, and having pairs of cells, each cell having a control gate, a floating gate and a source/drain diffusion, a first cell of each of said pairs having a first value of floating-gate to diffusion capacitance, a second cell of each of said pairs having a second value of floating-gate to diffusion capacitance, said memory comprising;

• a first circuit for applying a first erasing pulse to each of said control gates and said diffusions of said first cells of said pairs;
• a second circuit for applying a second erasing pulse to each of said control gates and said diffusions of said second cells of said pairs, said first erasing pulse adjustable to have a different magnitude than said second erasing pulse to narrow the distribution of threshold voltage caused by any difference between said first value and said second value;
• and
• said first and second circuits including an input for decoding each cell of said pair, each of said first and second circuits including at least one isolation transistor for isolating said decoding input from one of said first and second erasing pulses.

A method for obtaining a narrow margin of voltage thresholds in a nonvolatile memory having pairs of cells, said memory having at least a first and a second reference voltage, each pair of cells having a first cell and a second cell, each said first and second cell having a control gate, a floating gate and a source/drain diffusion, said method comprising;

• applying a first erasing pulse to each of said control gates and said diffusions of said first cells of said pairs;
• applying a second erasing pulse to each of said control gates and said diffusions of said second cells of said pairs;
• and
• adjusting the relative magnitudes of said first and second erasing pulses by varying said first reference voltage applied to said control gates of said first cells to be different than said second reference voltage applied to said control gates of said second cells, said magnitudes adjusted to result in a narrower margin of threshold voltages where said first cell of each of said pairs has a first value of floating-gate to diffusion capacitance and where said second cell of each of said pairs has a second value of floating-gate to diffusion capacitance different from said first value.

A method for obtaining a narrow margin of voltage thresholds in a nonvolatile memory having pairs of cells, said memory having at least one reference voltage, each pair of cells having a first cell and a second cell, each said first and second cell having a control gate, a floating gate and a source/drain diffusion, said method comprising;

• applying a first erasing pulse to each of said control gates and said diffusions of said first cells of said pairs;
• applying a second erasing pulse to each of said control gates and said diffusions of said second cells of said pairs;
• adjusting the magnitudes of said first erasing pulse and said second erasing pulse to narrow the margin of erased threshold voltages where said first cell of each of said pairs has a first value of floating-gate to diffusion capacitance and where said second cell of each of said pairs has a second value of floating-gate to diffusion capacitance different from said first value;
• said first and second erasing pulses generated by circuits including inputs for decoding each cell of each said pair;
• and
• said circuits including isolation transistors for isolating said decoding inputs from said first and second erasing pulses.