Semiconductor memory device having an improved error correction capability

Abstract

A semiconductor memory device which is comprised of a plurality m of electrically isolated data memory sub-arrays for storing data bits and a plurality k of electrically isolated parity memory sub-arrays for storing parity bits, wherein each of the data and parity memory sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row connected to a common word line and the memory cells in each column connected to a common bit line. Row address decoders function to activate a selected word line in each of the memory sub-arrays, and column address decoders, in combination with column selection circuitry, function to couple a selected bit line in each of the memory sub-arrays to a plurality m of sense amplifiers, which function to sense the voltage level of respective ones of the selected bit lines, and produce output data and parity bits representative of these sensed voltage levels. An error checking and correction circuit compares the output data and parity bits in order to detect and correct errors in the output data bits. Because of the unique architecture of the semiconductor memory device of this invention, defects in word lines or bit lines are confined to a single bit, thereby rendering these defects easily reparable by means of an ECC circuit alone, and thus dispensing with the need for a redundant memory circuit.

Dependencies are inferred from the claim text.