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US 5,313,418 AGranted
Semiconductor memory and memorizing method to read only semiconductor memory
AssigneeNippon Steel Corporation
InventorsToshio Wada, Yuichi Egawa
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AssigneeNippon Steel Corporation
InventorsToshio Wada, Yuichi Egawa
Estimating the term…
A mask ROM of the invention comprises: a plurality of memory cells arranged m a matrix; a plurality of word lines, each connecting gates of the memory cells in the lateral direction; a plurality of bit lines which are constructed by serially connecting MOS transistors constructing the memory cells; a row decoder connected to the word lines; and a column decoder connected to the bit lines in which each memory cell is constructed by an MOS transistor and a resistor connected in parallel between the source and drain of each MOS transistor. The content of each memory cell is determined by whether the resistor 8 is cut out or not so that the steps up to the cutting step of the resistors 8 can be standardized while maintaining a high density in integration of the memory cells and the turn-around time can be reduced.
A semiconductor memory device comprising:
A semiconductor memory device comprising:
A method of writing data into a semiconductor memory device comprising a switching element group which is arranged in a plurality of columns, each including a plurality of switching elements, each having a control terminal and a current path, the current paths of the switching elements of each column being connected in series, a plurality of row lines each being connected to the control terminals of corresponding switching elements of the respective columns, a column decoder connected to the switching elements of the respective columns for selecting the switching elements connected in one of the columns, and a row decoder connected to said plurality of row lines for selecting one of the row lines, said method comprising the steps of:
A method of storing data into a semiconductor memory device comprising a switching element group which is arranged in a plurality of columns, each including a plurality of switching elements, each switching element having a control terminal and a current path, the current paths of the switching elements of each column being connected in series, a plurality of row lines, each being connected to the control terminals of corresponding switching elements of the respective columns, a column decoder connected to the switching elements of the respective columns for selecting the switching elements connected in one of the columns, a row decoder connected to said plurality of row lines for selecting one of the row lines, and impedance means connected in parallel to the current path of each of the switching elements in each column, said method comprising the steps of:
Dependencies are inferred from the claim text.