Oversampling type finite impulse responsive filter
AssigneeAdvantest Corporation
InventorYoshihiro Nukui
Life of this patent
Estimating the term…
Abstract
Digital data provided in the form of a serial signal is fetched into an N-bit shift register and parallel N-bit data output therefrom is provided as address data to address input terminals of a memory. In the memory there are prestored at respective addresses defined by the N-bit data the total sum value of multiplied outputs obtained by multiplying the address values and the bit data of a coefficient h(n-i) defining an impulse response characteristic. The N-bit data is provided to an address input terminal of the memory to read out therefrom a digital value corresponding to the output voltage of a digital filter. The digital value is D/A converted to obtain the output voltage of the digital filter.
Claims6
A digital filter comprising:
- M-bit shift register means, for sequentially receiving pieces of an input pulse train signal having a fixed symbol rate in synchronization with a first clock equal to the symbol rate of said input pulse train signal, M being the smallest integer larger than N/K, N being an integer defined substantially by N=2n+1, where n is a positive integer, and K is an integer greater than 1;
- counter means for resetting upon each counting of K second clocks of a rate K times higher than that of said first clock;
- memory means for receiving, as a readout address, a combination of outputs expressed by Q(0), Q(1), . . . Q(M-1), from respective shift stages of said shift register means and a count output of said counter means expressed by C(0), C(1), . . . C(K-1), where k is an integer greater than 1, said memory means having stored at each address a value of a total sum of N multiplied values defined by ##EQU10## where C is a decimal value of the count output C(0), . . . C(k-1), h(i-n) represents an ith one of 2n+1 coefficients defining a predetermined impulse response of an N-order filter, and (i-C)/k represents a smallest integer larger than (i-C)/K;
- and
- D/A converting means for converting the value of said total sum read out of said memory means to an analog signal.
A digital filter comprising:
- M-bit shift register means sequentially supplied with pieces of an input pulse train signal of a fixed symbol rate in synchronization with a first clock equal to the symbol rate, M being the smallest integer larger than N/K, N being an integer defined substantially by N=2n+1, where n is a positive integer and K being an integer greater than 1, said M-bit shift register means defining m serial groups of stages, m being an integer equal to or greater than 2, the number of shift stages in respective m groups being represented by M.sub.1, M.sub.2, . . . M.sub.m, and said m groups providing outputs Q(0), Q(1), . . . Q(M.sub.1 -1);
- Q(0), Q(1) . . . Q(M.sub.2 -1);
- . . . Q(0), Q(1) . . . Q(M.sub.m -1);
- counter means reset upon each counting of K second clocks having a rate K times higher than that of said first clock and providing a count output of k bits represented by C(0), C(1) . . . C(k-1), k being an integer greater than 2;
- m split memories each for receiving a combination of outputs from corresponding ones of said m shift stage groups and said count output from said counter means as a readout address, each of said m split memories prestoring at each address thereof a partial sum value defined by ##EQU11## where C is a decimal value of the count output C(0), C(1) . . . C(k-1), h(i-n) represents an ith one of 2n+1 coefficients defining a predetermined impulse response of an N-order filter, and (i-C)/K represents the smallest integer larger than (i-C)/K;
- adding means for calculating a total sum value of the partial sums read out from said m split memories;
- and
- D/A converting means for converting the total sum value from said adding means to an analog signal.
Dependencies are inferred from the claim text.