Chroma processor including a look-up table or memory

A digital chroma processor for generating first key signals in response to first chrominance signals, and second chrominance signals, the chroma processor comprising:

• user interface means for selecting color modification parameters;
• memory means for holding the first key signals for the first and second chrominance signals, the memory means providing the first key signals when addressed by the first and second chrominance signals;
• and
• processing means for generating the first key signals in accordance with the selected color modification parameters, the processing means loading the memory means with the first key signals.

A digital chroma processor for providing new luminance signals in response to first chrominance signals, second chrominance signals, and luminance signals, the chroma processor comprising:

• means for generating color modification parameters;
• first look-up table means for storing the new luminance signals for a plurality of the first chrominance signals, the second chrominance signals, and the luminance signals, the first look-up table means providing the new luminance signals when addressed by the first and second chrominance signals and the luminance signals;
• and
• processing means for generating the new luminance signals in accordance with the color modification parameters and loading the first look-up table means with the new luminance signals.

A digital chroma processor, comprising:

• a first input for receiving first chrominance values;
• a second input for receiving second chrominance values;
• a user interface;
• a processor coupled to the user interface, wherein the processor produces a new first chrominance value and a new second chrominance value for each first and second chrominance value in a set of first and second chrominance values in response to commands from the user interface;
• a memory having data outputs and first address inputs and data inputs, the first address inputs and data inputs coupled to the processor, the memory storing the new first and new second chrominance values on the data inputs for each first and second chrominance value in the set of first and second chrominance values at memory locations addressed by corresponding ones of the first and second chrominance values of the set of the first and second chrominance values, the memory having second address inputs coupled to the first input and the second input for receiving the first and second chrominance values, the memory providing the new first and second chrominance values at the data outputs in response to the first and second chrominance values on the second address inputs.

A digital chroma processor, comprising:

• a first input for receiving first chrominance values;
• a second input for receiving second chrominance values;
• a user interface;
• a processor coupled to the user interface, wherein the processor produces key values for each first and second chrominance value in a set of first and second chrominance values in response to commands from the user interface;
• a memory having data outputs and first address inputs and data inputs, the first address inputs and the data inputs being coupled to the processor, the memory storing the key values on the data inputs for each first and second chrominance value in the set of first and second chrominance values at memory locations addressed by corresponding ones of the first and second chrominance values of the set of the first and second chrominance values, the memory having second address inputs coupled to the first and second inputs, the memory providing the key values at the data outputs in response to the first and second chrominance values on the second address inputs.

A digital chroma processor for providing first output chrominance signals and second output chrominance signals in response to first input chrominance signals and second input chrominance signals, the chroma processor comprising:

• a user interface;
• a processor;
• a memory, the memory storing the first output chrominance signals and the second output chrominance signals, the memory providing the first output chrominance signals and the second output chrominance signals in response to the first input chrominance signals and the second input chrominance signals;
• and
• wherein the processor is coupled to the user interface, the processor producing the first output chrominance signals and the second output chrominance signals for storage in the memory in response to commands from the user interface.

A digital chroma processor for generating key signals in response to first input chrominance signals and second input chrominance signals, the chroma processor comprising:

• a user interface;
• a processor;
• a memory, the memory storing the key signals, the memory providing the key signals in response to the first input chrominance signals and the second input chrominance signals;
• and
• wherein the processor is coupled to the user interface, the processor producing the key signals for storage in the memory in response to commands from the user interface.

A digital chroma processor for generating key signals in response to input luminance signals, the chroma processor comprising:

• a user interface;
• a processor;
• a memory, the memory storing the key signals, the memory providing the key signals in response to the input luminance signals;
• and
• wherein the processor is coupled to the user interface, the processor producing the key signals for storage in the memory in response to commands from the user interface.