Demodulation processing circuit with time interval counting feature
AssigneeCanon Kabushiki Kaisha
InventorKazuhiro Izukawa
Life of this patent
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Abstract
In a demodulation circuit for demodulating a pulse position modulation (PPM) signal, and a camera having the demodulation circuit, a change in PPM signal is counted by an up/down counter which is switched between count-up and count-down modes every time the PPM signal changes. When a carry signal is output from the counter, the carry signal is latched, and the PPM signal is demodulated into binary data on the basis of the presence/absence of the carry signal in the count-up mode and the carry signal in the count-down mode.
Claims6
A camera having a data processing apparatus for determining data on the basis of an interval between trailing and leading edge positions of a continuous signal, comprising:
- (a) a processing circuit having count means for counting a time interval between the trailing edge timing and the leading edge timing of the signal in a first direction, said count means generating a first signal when a count value of said count means reaches a predetermined count value within the time interval, said processing circuit having a first function of latching the first signal, and a second function of causing said count means to count a time interval between the leading edge timing and the trailing edge timing of the signal from the predetermined count value in a direction opposite to the first direction, and judging whether or not the count value of said count means reaches a predetermined second count value, and said processing circuit determining data on the basis of the latched first signal and a judgment result of the second function.
A camera having a data processing apparatus for determining data on the basis of an interval between trailing and leading edge positions of a continuous signal, comprising:
- (a) count means for counting a first time interval between the trailing edge timing and the leading edge timing of the signal, and a second time interval between the leading edge timing and the trailing edge timing of the signal;
- and
- (b) a processing circuit for detecting whether or not a count amount counted within the first time interval reaches a predetermined value and whether or not a count amount counted within the second time interval reaches a predetermined value, and determining data on the basis of detection results in the first and second time intervals.
Dependencies are inferred from the claim text.