Capacity ground type filter circuit

A filter circuit comprising:

• a first integrator comprising a first differential amplifier which receives an input signal at a non-inverting input;
• a second integrator comprising a second differential amplifier which receives an output of said first differential amplifier at a non-inverting input;
• the outputs of said first and second differential amplifiers being fed back to an inverting input of said first differential amplifier and being input to an inverting input of a subtracter;
• and
• said subtracter comprising a third differential amplifier for outputting the difference between said input signal received at a non-inverting input and said outputs of said first and second differential amplifiers received at an inverting input;
• wherein said filter circuit comprises a high pass filter circuit with an output of said subtracter only containing the high frequency components of said input signal.

A filter circuit comprising:

• a plurality of integrators in the number of N, where N.gtoreq.2 with at least a first integrator and a second integrator respectively having a first and second differential amplification circuits connected in series with each other with an output of said first differential amplification circuit being input to said second differential amplification circuit;
• and
• a subtracter comprising a differential amplification circuit for subtracting output signals of said integrators from an input signal and for outputting the results of the subtraction as a filter output signal;
• wherein said filter circuit is a high pass filter circuit with said filter output signal only comprising the high frequency components of said input signal.

An integrator comprising:

• first and second transistors forming a differential amplifier with an emitter of said first transistor connected to an emitter of said second transistor;
• third and fourth transistors forming a load for said first and second transistors, wherein a collector of said third transistor is connected to a collector of said first transistor and a collector of said fourth transistor is connected to a collector of said second transistor;
• and
• said first and second transistors are sized relative to said third and fourth transistors so that a first stray capacitance is formed between ground and said collector of said second transistor and a second stray capacitance is formed between a source of power and said collector of said fourth transistor;
• wherein an input signal is received at a base of said first transistor and an integrated output signal is generated at said collector of said second transistor and wherein said first stray capacitance and said second stray capacitance are formed with offsetting voltage characteristics.

An integrator comprising:

• first and second transistors forming a differential amplifier with an emitter of said first transistor connected to an emitter of said second transistor;
• third and fourth transistors forming a load for said first and second transistors, wherein a collector of said third transistor is connected to a collector of said first transistor and a collector of said fourth transistor is connected to a collector of said second transistor;
• a first parasitic capacitance formed between ground and said collector of said second transistor;
• and
• a second parasitic capacitance formed between a source of power and said collector of said fourth transistor;
• wherein an input signal is received at a base of said first transistor and an integrated output signal is generated at said collector of said second transistor and said first and second transistors are sized to be twice as large as said third and fourth transistors so that said first parasitic capacitance and said second parasitic capacitance are formed with offsetting voltage characteristics.