Address buffer with ATD generation

An address buffer for generating an ATD (address transition detection) pulse, comprising:

• a differential amplifier, having first and second resistors, and first and second bipolar transistors, the first resistor being coupled between a first power supply voltage terminal and a collector of the first bipolar transistor, the second resistor being coupled between the first power supply voltage terminal and a collector of the second bipolar transistor, the differential amplifier for receiving an address signal having first and second logic states;
• a first MOS transistor having a first current electrode coupled to the collector of the first bipolar transistor, a second current electrode, and a gate for receiving a first delayed control signal;
• a second MOS transistor having a first current electrode coupled to the collector of the second bipolar transistor, a second current electrode, and a gate for receiving a second delayed control signal;
• a first emitter-follower transistor having a collector coupled to the first power supply voltage terminal, a base coupled to the second current electrodes of both the first and second MOS transistors, and an emitter for providing the ATD pulse;
• a second emitter-follower transistor having a collector coupled to a power supply voltage terminal, a base coupled to the collector of the first bipolar transistor, and an emitter for providing a first buffered logic signal;
• a third emitter-follower transistor having a collector coupled to the power supply voltage terminal, a base coupled to the collector of the second bipolar transistor, and an emitter for providing a second buffered logic signal;
• and
• a level converter for receiving the first and second buffered logic signals and for providing the first and second delayed control signals.

An address buffer with ATD (address transition detection) generation, comprising:

• a differential amplifier, having first and second resistors, and first and second bipolar transistors, the first resistor being coupled between a power supply voltage terminal and a collector of the first bipolar transistor, the second resistor being coupled between the power supply voltage terminal and a collector of the second bipolar transistor, the differential amplifier for receiving an ECL level address signal having first and second logic states;
• a first P-channel transistor having a first current electrode coupled to the collector of the first bipolar transistor, a second current electrode, and a gate for receiving a first delayed control signal;
• a second P-channel transistor having a first current electrode coupled to the collector of the second bipolar transistor, a second current electrode, and a gate for receiving a second delayed control signal;
• a first emitter-follower transistor having a collector coupled to the power supply voltage terminal, a base coupled to the second current electrodes of both the first and second P-channel transistors, and an emitter for providing an ATD pulse when the ECL level address signal transitions from the first logic state to the second logic state;
• a second emitter-follower transistor having a collector coupled to the power supply voltage terminal, a base coupled to the collector of the first bipolar transistor, and an emitter for providing a first buffered logic signal;
• and
• a third emitter-follower transistor having a collector coupled to the power supply voltage terminal, a base coupled to the collector of the second bipolar transistor, and an emitter for providing a second buffered logic signal.