Field programmable gate array
AssigneeCrosspoint Solutions, Inc.
InventorsLaurence H. Cooke, David Marple
Life of this patent
Estimating the term…
Abstract
A FPGA matching the organization and performance of mask programmable gate arrays is presented. The core array is organized into rows of continuous series transistors (CSTs) and rows of small latch/logic blocks. The source/drains and gate of each of the transistors are connected to line segments. The input and output terminals of the blocks are also connected to line segments. Programmable antifuses are located at the intersections of the line segments, which also include others for power and routing purposes. The FPGA can be efficiently configured into a user's application with the flexibility of the CSTs and the efficiency of the latch/logic blocks, which may also be configured into RAM arrays.
Claims42
A field programmable gate array integrated circuit in a semiconductor substrate, comprising
- an array of at least four MOS transistors, each transistor having first and second source/drains in said substrate and a gate separating said first and second source/drains, said transistors connected in series with a first source/drain of one transistor merging into a second source/drain of another transistor;
- a plurality of conducting line segments, each of said first and second source/drains and each of said gates connected to one of said line segments;
- and
- a plurality of antifuses located at intersections of said conducting line segments, said conducting line segments connectable to each other at said intersections by the programming of antifuses therebetween;
- whereby said array of MOS transistors are configurable into a desired circuit by programming selected antifuses.
An field programmable gate array integrated circuit comprising
- a plurality of conducting line segments, said conducting line segments intersecting each other and having antifuses at said intersections, said conducting line segments connectable to each other at said intersections by the programming of antifuses therebetween;
- means for programming said intersecting conducting line segments by a plurality of local decode logic circuits controlled by signals on two or more lines spanning said array in perpendicular directions, said local decode logic circuits controlling programming transistors driven by a plurality of programming wires spanning said array in perpendicular directions;
- whereby a selected antifuse between a selected pair of said conducting line segments is programmed.
A field programmable logic array having
- a plurality of conducting lines in a first direction and a plurality of conducting lines in a second direction perpendicular to said first direction;
- and
- an array of circuit blocks located at the intersections of said first and second direction conducting lines and connected to said conducting lines, each of said circuit blocks also connected to wiring segments, said wiring segments interconnectable through programmable antifuses, each block configurable to perform a logic function or a latching function by selectively interconnecting said wiring segments through programming said antifuses so that said array of circuit blocks is operable jointly or separately responsive to signals upon said conducting lines.
An integrated circuit having an array of circuit blocks, said array comprising
- a plurality of conducting lines in a first direction and a plurality of conducting lines in a second direction, each of said conducting lines connected to each circuit block in said array;
- a plurality of conducting line segments, said conducting line segments intersecting each other and having antifuses at said intersections, said conducting line segments connectable to each other at said intersections by the programming of antifuses therebetween;
- and
- each of said circuit blocks further connected to said conducting line segments, the operations of each of said circuit blocks defined into logic and latch functions by selectively interconnecting said conducting line segments through programmed antifuses;
- whereby said circuit blocks and said array are configurable by programming selected antifuses.
A field programmable gate array integrated circuit, comprising
- a plurality of conducting line segments, said conducting line segments intersecting each other and having antifuses at said intersections, said conducting line segments connectable to each other at said intersections by programmed antifuses therebetween;
- a plurality of programming transistors, each conducting line segment connected to one of said programming transistors selectively activated by local decode logic circuits responsive to control lines spanning said array in perpendicular directions;
- a plurality of programming wires spanning said array in perpendicular directions, each programming transistor selectively driven through one of said programming wires;
- whereby an antifuse between a first and second conducting line segment is programmed by selectively activating programming transistors connected to said first and second conducting line segments and selectively driving said programming transistors connected to said first and second conducting line segments.
Dependencies are inferred from the claim text.