High-speed, low-noise, CMOS output driver

An output circuit, comprising:

• a) a first pull-down transistor and a pull-up transistor, each of said transistors having a source-to-drain path and a gate;
• the source-to-drain path of said pull-up transistor being connected between another terminal of a voltage supply and an output node;
• the source-to-drain path of said first pull-down transistor being connected between another terminal of said voltage supply and said output node;
• the gate of said first pull-down transistor being connected to a logic voltage driver;
• b) a second pull-down transistor having a source-to-drain path and a gate;
• the source-to-drain path of said second pull-down transistor being connected between another terminal of said voltage supply and said output node;
• said first pull-down transistor being smaller than said second pull-down transistor;
• c) a pair of complementary transistors having source-to-drain paths connected at a source-to-drain path series connection point and in series between said output node and said another terminal of said supply, the gates of said complementary transistors being connected to an inverse of said logic voltage driver, said source-to-drain path series connection point connected to the gate of said second pull-down transistor;
• and
• d) a pass transistor having a source-to-drain path connected between said output node and the gate of said second pull-down transistor and having a gate connected to said logic voltage driver.

An output circuit, comprising:

• a) a first pull-down transistor, a first series transistor, and a pull-up transistor;
• each of said transistors having a source-to-drain path and a gate;
• the source-to-drain path of said pull-up transistor being connected between one terminal of a voltage supply and an output node;
• the source-to-drain paths of said first series transistor and said first pull-down transistor being connected in series between said output node and another terminal of said voltage supply;
• the gate of said first series transistor being connected to said one terminal of said supply;
• b) a second pull-down transistor, a second series transistor, and a coupling transistor, each of said transistors having a source-to-drain path and a gate;
• the source-to-drain paths of said second pull-down transistor and said second series transistor being connected in series between another terminal of said voltage supply and said output node;
• the gates of said first and second pull-down transistors being connected to a logic voltage driver;
• the gate of said second series transistor being connected to said output node through the source-to-drain path of said coupling transistor;
• the gate of said coupling transistor being connected to said one terminal of said supply;
• said first pull-down transistor being smaller than said second pull-down transistor.