Semiconductor power device having walls of an inverted mesa shape to improve power handling capability

A semiconductor power device of a vertical arrangement having a high withstanding voltage and including a region formed of a high-resistance layer with a predetermined impurity density and a low-resistance layer whose impurity density is higher than that of the high-resistance layer, comprising:

• a first semiconductor substrate forming the high-resistance layer having first and second opposite surfaces;
• a second semiconductor substrate forming the low-resistance layer having first and second opposite surfaces, the second surface of the first semiconductor substrate being joined to the first surface of the second semiconductor substrate at a joined area;
• at least a first electrode, connected to said first surface of said first semiconductor substrate;
• at least a second electrode, connected to said second surface of said second semiconductor substrate, such that a current flow between said first and second electrodes is in a vertical direction from said first surface of said first semiconductor substrate to said second surface of said second semiconductor substrate;
• a PN junction formed by diffused impurities having electrical characteristics different from those of impurities contained in the high-resistance layer, from said first surface of the first semiconductor substrate,
• the periphery of the first semiconductor substrate being defined by oblique side faces including at least edges of the PN junction, the oblique side faces being so inclined that a cross-sectional area of the first semiconductor substrate is reduced toward the joined area of the first and second semiconductor substrates and that, on sides of the first and second semiconductor substrates at said joined area, a surface area of the second semiconductor substrate is larger than a surface area of the first semiconductor substrate, wherein said oblique side faces are inclined at a minimum necessary angle that an electric field intensity at said edges of the PN junction when a reverse bias is applied thereto and an electric field intensity of an interface between the high-resistance layer and the low-resistance layer when a reverse bias is applied thereto are each smaller than an electric field intensity at a central area of the PN junction when a reverse bias is applied thereto;
• an insulation material layer coating said side surface and part of said third main face of said second semiconductor substrate to form an indented insulated area on an open side surface of said insulation material layer between insulation material layers of said side surface and said part of said third main face of said second semiconductor substrate.

A semiconductor power transistor of a vertical arrangement having a high withstanding voltage and including a region formed of a high-resistance layer with a predetermined impurity density and a low-resistance layer whose impurity density is higher than that of the high-resistance layer, comprising:

• a first semiconductor substrate of monocrytalline silicon, having a first conductivity type and having one main face and an opposite main face, the high-resistance layer being of a different conductivity type and formed in the first semiconductor substrate adjacent to the opposite main face, a PN junction forming a boundary of the high-resistance layer from the one main face toward the inside of the first semiconductor substrate, said first semiconductor substrate including a region of said different conductivity type in said one main face;
• a second semiconductor substrate of monocrystalline silicon, forming the low-resistance layer, and having a first main face joined to the opposite main face of the first semiconductor substrate, and a second main face, opposite the first main face;
• at least a first electrode, connected to said first semiconductor substrate on said one main face of said first semiconductor substrate at a part other than where said region is located;
• at least a second electrode, connected to said second main face of said second semiconductor substrate, such that a current flow between said first and second electrodes is from said one main face of said first semiconductor substrate to said second main face of said second semiconductor substrate;
• a third electrode connected to said region,
• said second and third electrodes forming emitter and collector electrodes of said transistor and said first electrode forming a base electrode thereof;
• at least one edge of the PN junction being defined by at least one oblique side face that is inclined such that a cross-sectional area of the first semiconductor substrate is reduced from the one main face toward the opposite main face and covered with an insulating film, on the other side of which is a gap in which no impurity-doped material is disposed, and such that, where the first and second semiconducting substrates are joined, a surface area of the second semiconductor substrate being larger than a surface area of the first semiconductor substrate and a part where said second semiconductor substrate is larger being covered with an insulating film, and wherein said at least one oblique side face is inclined such that an electric field intensity at a periphery of the PN junction when a reverse bias is applied thereto and an electric field intensity at an interface between the high-resistance layer and the low-resistance layer when a reverse bias is applied thereto are each smaller than an electric field intensity at as central area of the PN junction when a reverse bias is applied thereto.

A semiconductor power transistor of a vertical arrangement having a high withstanding voltage and including a region formed of a high-resistance layer with a predetermined impurity density and a low-resistance layer whose impurity density is higher than that of the high-resistance layer, comprising:

• a first semiconductor substrate of monocrystalline silicon forming the high-resistance layer having first and second opposite surfaces, said first semiconductor substrate including a region of said different conductivity type in said first surface;
• a second semiconductor substrate of monocrystalline silicon forming the low-resistance layer having first and second surfaces, the second surface of the first semiconductor substrate being joined to the first surface of the second semiconductor substrate at a joined area;
• and
• at least a first electrode, connected to said first surface of said first semiconductor substrate, said first electrode being connected to a part of said first surface other than where said region is located;
• at least a second electrode, connected to said second surface of said second semiconductor substrate, such that a current flow between said first and second electrode is from said first surface of said first semiconductor substrate to said second surface face of said second semiconductor substrate;
• a third electrode connected to said region,
• said second and third electrodes forming emitter and collector electrodes of said transistor and said first electrode forming a base electrode thereof;
• a PN junction formed by diffusing impurities having electrical characteristics different from those of impurities contained in the high-resistance layer, from said first surface of the first semiconductor substrate,
• the periphery of the first semiconductor substrate being defined by oblique side faces including at least edges of the PN junction, the oblique side faces being so inclined that a cross-sectional area of the first semiconductor substrate is reduced toward the joined area of the first and second semiconductor substrates and covered with an insulating film, on the other side of which is a gap in which no doped material is disposed, and that, on sides of the first and second semiconductor substrates at said joined area, a surface area of the second semiconductor substrate is larger than a surface area of the first semiconductor substrate and a part where said second semiconductor substrate is larger being covered with an insulating film, and wherein said oblique side faces are inclined such that an electric field intensity at the periphery of the PN junction when a reverse bias is applied thereto and an electric field intensity of an interface between the high-resistance layer and the low-resistance layer when a reverse bias is applied thereto are each smaller than an electric field intensity at a central area of the PN junction when a reverse bias is applied thereto.