R.F. switching circuits

An r.f. switch having a common terminal and at least a pair of branch terminals comprising:

• a plurality of metal semiconductor field effect transistors, each transistor having source, drain, and gate electrodes arranged to provide a low impedance path between said common terminal and a first one of said branch terminals and a high impedance path between said common terminal and a second one of said branch terminals in response to a first state of a control signal fed to the gate electrode of said transistors, and a low impedance path between said second branch terminal and said common terminal and a high impedance path between said common terminal and said first branch terminal in response to a second, different state control signal fed to the gate electrodes of said transistors, each of said metal semiconductor field effect transistors comprising:
• an active region, comprising doped gallium arsenide supported by said substrate;
• a plurality of drain electrode portions disposed in ohmic contact over said active region and spaced along said active region;
• a second plurality of source electrode portions disposed in ohmic contact over said active region and spaced along said active region from said electrode portions to provide gate regions of said active layer;
• a third plurality of gate electrodes extending along a first direction and disposed in Schottky barrier contact with said active region, with each one of said third plurality of gate electrodes having first and second ends and each of said electrodes being disposed on one of said gate regions of said active region;
• and
• a plurality of interconnect sections extending along a direction perpendicular to the first direction and disposed between the source and drain electrodes in Schottky barrier contact with said active region, to interconnect said third plurality of gate electrodes in a series circuit, with a first one of said pluraliyt of interconnect sections, connected between respective first ends of an adjacent pair of said third plurality of gate electrodes, and with a second one of said plurality of interconnect sections connected to a second end of one of said pair of adjacent gate electrodes and to a corresponding second end of a succeeding one of said plurality of gate electrodes disposed adjacent said one of said pair of adjacent gate electrodes, said gate electrodes and interconnecting sections controlling the flow of carriers between the source and drain electrodes in both the first direction and in the direction perpendicular to the first direction.