Circuit for compressing digital images while retaining image fidelity

An image compressing circuit which is comprised of:

• a video input circuit for producing first electrical input signals which represent a digital input image that is made of multiple rows of X-bit pixels;
• a number generating circuit, coupled to said video input circuit, which generates second electrical input signals that identify a respective number for each X-bit pixel in said input image such that across each row the numbers occur as a particular number series which cyclically repeats;
• a translator circuit, coupled to said video input circuit and number generating circuit, which performs a translation on each individual X-bit pixel together with its respective number to produce an electrical output signal that represents a corresponding Y-bit pixel, where Y is less than X and more than one;
• and,
• said translation, when performed sequentially on consecutive X-bit pixels of a single magnitude in a row for two cycles of said numbers, producing two identical series of said Y-bit pixels with a) all of said Y-bit pixels within a series having only one or two magnitudes and b) said Y-bit pixel series having an average value that increases monotonically as said single magnitude increases.