Timing generation in an automatic electrical test system
AssigneeLTX Corporation
InventorsTimothy Alton, R. Warren Necoechea
Life of this patent
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Abstract
A method and apparatus for generating timing markers in an automatic electrical test system. Timing parameters are synchronized by an external period start signal corresponding to a centrally generated external period and an internal period start signal generated locally for each input/output pin. The timing parameters comprise T1 counter and vernier values, T2 counter and vernier values, and period-minus-T1 counter and period vernier values.
Claims27
A method for generating timing markers in an automatic electrical test system, comprising the steps of:
- receiving a first set of timing parameters corresponding to a first external period start, the first set of timing parameters comprising a first T1 value, a first T2 value, and a first period-minus-T1 value;
- generating a first internal period start, the first internal period start offset from the first external period start by the first T1 value;
- generating a first T1 marker and a first T2 marker, the first T1 marker offset from the first external period start by the first T1 value, the first T2 marker offset from the first internal period start by the first T2 value.
An apparatus for generating timing markers in an automatic electrical test system, comprising:
- means for receiving a first set of timing parameters corresponding to a first external period start, the first set of timing parameters comprising a first T1 value, a first T2 value, and a first period-minus-T1 value;
- means for generating a first internal period start, the first internal period start offset from the first external period start by the first T1 value;
- means for generating a first T1 marker and a first T2 marker, the first T1 marker offset from the first external period start by the first T1 value, the first T2 marker offset from the first internal period start by the first T2 value.
A circuit for generating T1 and T2 timing markers in an automatic electrical test system, comprising:
- first-in-first-out memory means coupled to receive and store a timing parameter address, the timing parameter address synchronized by an external period signal;
- memory means storing a plurality of timing parameter entries, the memory means coupled to receive the timing parameter address from the first-in-first-out memory means, the timing parameter address synchronized by an internal period signal, the timing parameter address selecting one of the timing parameter entries;
- adder circuit coupled to receive the timing parameter entries, the adder circuit generating a T1 marker value and a T2 marker value;
- counter circuit coupled to receive the T1 marker value and the T2 marker value, the counter circuit generating the internal period signal, the T1 marker, and the T2 marker.
Dependencies are inferred from the claim text.