Semiconductor memory device having a CMOS decoding circuit

A semiconductor memory device receiving a first and a second pair of input signals, each of said pairs of input signals including a first address signal having a predetermined phase and a second address signal, the first and second address signals of each of said first and second pairs of input signals being complementary and substantially in phase with each other, the semiconductor memory device comprising:

• a plurality of floating gate type memory cells, each having a first, a second and a gate electrode, said memory cells storing data;
• a plurality of word lines, each being coupled to the gate electrodes of said memory cells;
• a plurality of bit lines, each being coupled to the first electrodes of said memory cells;
• a plurality of first source lines, each being coupled to the second electrodes of said memory cells;
• a plurality of source line switches, each having a control terminal, each of said source line switches being coupled between a second source line and one of said first source lines;
• a data bus for transferring the data read from said memory cells;
• a plurality of first column switches, each having a control terminal ,each of said first column switches being coupled between said data bus and one of said bit lines;
• a plurality of second column switches, each having a control terminal connected to control terminal of a corresponding first column switch, each of said second column switches being coupled between a reference potential and one of said first source lines;
• and
• a control circuit having a first, a second, a third and a fourth input terminal and a first and a second output terminal connected to the control terminals of said source line switches and said column switches, said control circuit receiving the first address signal of the first pair of input signals through the first input terminal, the second address signal of the first pair of input signals through the second input terminal, the first address signal of the second pair of input signals through the third input terminal and the second address signal of the second pair of input signals through the fourth input terminal and outputting first and second control signals from the first and the second output terminals respectively, said control circuit comprising:
• a NAND gate having a first and a second input terminal coupled to the first and third input terminals of said control circuit respectively, and an output terminal coupled to the first output terminal of said control circuit;
• and
• a NOR gate having a first and a second input terminal coupled to the second and fourth input terminals of said control circuit respectively, and an output terminal coupled to the second output terminal of said control circuit, the first and second control signals being complementary and substantially in phase with each other.

A decoder circuit receiving a first and a second pair of input signals, each of said pairs f input signals including a first address signal having a predetermined phase and a second address signal, the first and second address signals of each of said first and second pairs of input signals being complementary and substantially in phase with each other, the decoder circuit comprising:

• a first input terminal for receiving the first address signal of the first pair of input signals;
• a second input terminal for receiving the second address signal of the first pair of input signals;
• a third input terminal for receiving the first address signal of the second pair of input signals;
• a fourth input terminal for receiving the second address signal of the second pair of input signals;
• a NAND gate having a first and a second input coupled to the first and third input terminals respectively and an output for outputting a first pre-decode signal;
• a NOR gate, electrically isolated from said NAND gate, having a first and a second input coupled to the second and fourth input terminals respectively and an output for outputting a second pre-decode signal, the first and second pre-decode signals being complementary and substantially in phase with each other;
• a first output terminal coupled to the output of said NAND gate;
• and
• a second output terminal coupled to the output of said NOR gate.

A semiconductor memory device receiving a first and a second pair of input signals, each of said pairs of input signals including a first address signal having a predetermined phase and a second address signal, the first and second address signals being complementary and substantially in phase with each other, the semiconductor memory comprising:

• a pre-decoder for receiving the first and second pairs of input signals and outputting first and second pre-decode signals, said pre-decoder comprising:
• a NAND gate having input terminals for receiving the first address signal of the first pair of input signals and the first address signal of the second pair of input signals, and having a first pre-decode output terminal for outputting the first pre-decode signal;
• and
• a NOR gate having input terminals for receiving the second address signal of the first pair of input signals and the second address signal of the second pair of input signals, and having a second pre-decode output terminal for outputting the second pre-decode signal, the first and second pre-decode signals being complementary and substantially in phase with each other;
• a memory array having a plurality of bit lines, a plurality of word lines and a plurality of memory cells;
• a row decoder, coupled to the pre-decoder and to the plurality of word line of said memory array, for selecting one of the plurality of word lines in response to the first and second pre-decode signals, said row decoder having a plurality of row decoder units each including:
• a gate circuit having an input terminal for receiving a further address signal, and an output terminal;
• and
• a plurality of word lines drivers, each having:
• a first MOS transistor of a first conductive type having a gate electrode coupled to the output terminal of the gate circuit, a first electrode coupled to the output terminal of the NAND gate of the pre-decoder and a second electrode coupled to a corresponding one of the plurality of word lines;
• a second MOS transistor of a second conductive type having a gate electrode coupled to the output terminal of the gate circuit, a first electrode coupled to a reference potential and a second electrode coupled to a corresponding one of the plurality of word lines;
• and
• a third MOS transistor of a second conductive type having a gate electrode coupled to the output terminal of the NOR gate of the pre-decoder, a first electrode coupled to the reference potential and a second electrode coupled to a corresponding one of the plurality of word lines.