Integrated circuit memory with asymmetric row access topology

An integrated circuit memory comprising:

• an array of memory cells arranged in a plurality of rows and at least one column;
• a first column line pair connecting memory cells in a column, said first column line pair divided into a first pair of column line halves and a second pair of column line halves;
• a second column line pair connecting memory cells in a column, said second column line pair divided into a third pair of column line halves and a fourth pair of column line halves;
• input/output means for connecting said first and second column lines pairs to a circuit external of said memory array, said input/output means connected to said second pair of column line halves and to said third pair of column line halves;
• a plurality of row lines, each row line connecting memory cells in a row;
• row access means for providing a row access signal defining a first row access cycle and a second row access cycle;
• timing signal generator means responsive to said row access signal for providing one or more isolation timing signals, wherein said isolation timing signals are derived from said row access signal;
• row decoder means responsive to said row access signal for addressing a row connected to a memory cell connected to said first pair of column line halves during said first row access cycle, for addressing a row connected to a memory cell connected to said second pair of column line halves during said second row access cycle, for addressing a row connected to a memory cell connected to said third pair of column line halves during said first row access cycle, and for addressing a row connected to a memory cell connected to said fourth pair of column line halves during said second row access cycle;
• a first N-sense amplifier connected to said first column line pair;
• a second N-sense amplifier connected to said second column line;
• first isolating means responsive to said one of said isolation timing signals for isolating said first N-sense amplifier from said first pair of column line halves during at least a portion of said second row access cycle, said first N-sense amplifier connected to said first pair of column line halves through said first isolating means;
• second isolating means responsive to one of said isolation timing signals for isolating said first N-sense amplifier from said second pair of column line halves during at least a portion of said first row access cycle, said first N-sense amplifier connected to said second pair of column line halves through said second isolating means;
• third isolating means responsive one of said isolation timing signals for isolating said second N-sense amplifier from said third pair of column line halves during at least a portion of said second row access cycle, said second N-sense amplifier connected to said third pair of column line halves through said third isolating means;
• and
• fourth isolating means responsive to one of said isolation timing signals for isolating said second N-sense amplifier from said fourth pair of column line halves during at least a portion of said first row access cycle said second N-sense amplifier connected to said fourth pair of column line halves through said fourth isolating means.

An integrated circuit memory comprising:

• an array of memory cells arranged in a plurality of rows and columns;
• a first column line pair of connecting memory cells in a column, said first column line pair divided into a first pair of column line halves and a second pair of column line halves;
• a second column line connecting memory cells in a column, said second column line divided into a third pair of column line halves and a fourth pair of column line halves;
• input/output means for connecting said column lines to a circuit external of said memory array, said input/output means connected to said second pair of column line halves and to said third pair of column line halves;
• a plurality of row lines, each row line connecting memory cells in a row;
• timing signal generator means for providing a timing signal defining a first time period and a second time period;
• row decoder means connected to said timing signal generator means for addressing a row connected to a memory cell connected to said first pair of column line halves during said first time period, for addressing a row connected to a memory cell connected to said second pair of column line halves during said second time period, for addressing a row connected to a memory cell connected to said third pair of column line halves during said first time period, and for addressing a row connected to a memory cell connected to said fourth pair of column line halves during said second time period;
• a first P-sense amplifier connected to said first pair of column line halves;
• a second P-sense amplifier connected to said second pair of column line halves;
• a third P-sense amplifier connected to said third pair of column line halves;
• a fourth P-sense amplifier connected to said fourth pair of column line halves;
• and
• first isolating means responsive to said timing signal generator means for isolating said second P-sense amplifier from said first pair of column line halves during at least a portion of said second time period;
• and
• second isolating means responsive to said timing signal generator means for isolating said third P-sense amplifier from said fourth pair of column line halves during at least a portion of said first time period.

An integrated circuit memory comprising:

• an array of memory cells arranged in a plurality of rows and columns;
• a first column line pair comprising a first column line connecting memory cells in one column and a second column line connecting memory cells in an adjacent column, said first column line pair divided into a first pair of column line halves and a second pair of column line halves;
• a second column line pair comprising a third column line connecting memory cells in one column and a fourth column line connecting memory cells in an adjacent column, said second column line pair divided into a third pair of column line halves and a fourth pair of column line halves;
• input/output means for connecting said column line pairs to a circuit external of said memory array;
• a plurality of row lines, each row line connecting memory cells in a row;
• row access means for providing a row access signal defining a first row access cycle and a second row access cycle;
• timing signal generator means responsive to said row access signal for providing one or more amplifier timing signals, wherein said amplifier timing signals are derived from said row access signal;
• row decoder means responsive to said row access signal for addressing a row connected to a memory cell connected to said first pair of column line halves during said first row access cycle, for addressing a row connected to a memory cell connected to said second pair of column line halves during said second row access cycle, for addressing a row connected to a memory cell connected to said third pair of column line halves during said first row access cycle, and for addressing a row connected to a memory cell connected to said fourth pair of column line halves during said second row access cycle;
• and
• first amplifier means responsive to one of said amplifier timing signals for amplifying a signal from a memory cell connected to said first pair of column line halves during said first row access cycle and for amplifying a signal from a memory cell connected to said second pair of column line halves during said second row access cycle, said first amplifier means drawing a first amount of power when amplifying said signal associated with said first pair of column line halves and as second amount of power different from said first amount of power when amplifying a signal from said second pair of column line halves;
• second amplifier means responsive to one of said amplifier timing signals for amplifying a signal from a memory cell connected to said third pair of column line halves during said first row access cycle and for amplifying a signal from a memory cell connected to said fourth pair of column line halves during said second row access cycle, said second amplifier means drawing said second amount of power when amplifying a signal associated with said third pair of column line halves and drawing said first amount of power when amplifying a signal associated with said fourth pair of column line halves.

An integrated circuit memory comprising:

• an array of memory cells arranged in a plurality of rows and at least one column;
• a first column line pair connecting memory cells in a column, said first column line pair divided into a first pair of column line halves and a second pair of column line halves;
• a second column line connecting memory cells in a column, said second column line divided into a third pair of column line halves and a fourth pair of column line halves;
• input/output means for connecting said first and second column lines to a circuit external of said memory array, said input/output means connected to said second pair of column line halves and to said third pair of column line halves;
• a plurality of row lines, each row line connecting memory cells in a row;
• row access means for providing a row access signal defining a first row access cycle and a second row access cycle;
• row decoder means responsive to said row access signal for addressing a row connected to a memory cell connected to said first pair of column line halves during said first row access cycle, for addressing a row connected to a memory cell connected to said second pair of column line halves in said second row access cycle, for addressing a row connected to a memory cell connected to said third pair of column line halves during said first row access cycle, and for addressing a row connected to a memory cell connected to said fourth pair of column line halves during said second row access cycle;
• a first P-sense amplifier connected to said first pair of column line halves;
• a second P-sense amplifier connected to said second pair of column line halves;
• a third P-sense amplifier connected to said third pair of column line halves;
• a fourth P-sense amplifier connected to said fourth pair of column line halves;
• timing signal generator means responsive to said row access signal for providing a refresh timing signal defining a refresh period, a first P-sense timing signal defining a P-sense period during said first row access cycle, a second P-sense timing signal defining a P-sense period during said second row access cycle, and one or more isolation timing signals, wherein said isolation timing signals are derived from said row access signal;
• first isolating means responsive to one of said isolation timing signals for isolating said first pair of column line halves from said second pair of column line halves during said P-sense period in said second row access cycle during said refresh period;
• second isolating means responsive to one of said isolation timing signals for isolating said second pair of column line halves from said first pair of column line halves during said P-sense period in said first row access cycle during said refresh period;
• third isolating means responsive to one of said isolation timing signals for isolating said third pair of column line halves from said fourth pair of column line halves during said P-sense period in said second row access cycle during said refresh period;
• and
• fourth isolating means responsive to one of said isolation timing signals for isolating said fourth pair of column line halves from said third pair of column line halves during said P-sense period in said first row access cycle during said refresh period.

An integrated circuit memory comprising:

• an array of memory cells arranged in a plurality of rows and at least one column;
• a first column line pair connected memory cells in a column, said first column line pair divided into a first pair of column line halves and a second pair of column line halves;
• a second column line pair connecting memory cells in a column, said second column line pair divided into a third pair of column line halves and a fourth pair of column line halves;
• input/output means for connecting said first and second column line pairs to a circuit external of said memory array, said input/output means connected to said first pair of column line halves and to said fourth pair of column line halves;
• a plurality of row lines, each row line connecting memory cells in a row;
• row access means for providing a row access signal defining a first row access cycle and a second row access cycle;
• timing signal generator means responsive to said row access signal for providing one or more isolation timing signals, wherein said isolation timing signals are derived from said row access signal;
• row decoder means responsive to said row access signal for addressing a row connected to a memory cell connected to said first pair of column line halves during said first row access cycle, for addressing a row connected to a memory cell connected to said second pair of column line halves during said second row access cycle, for addressing a row connected to a memory cell connected to said third pair of column line halves during said first row access cycle, and for addressing a row connected to a memory cell connected to said fourth pair of column line halves during said second row access cycle;
• a first N-sense amplifier connected to said first column line pair;
• a second N-sense amplifier connected to said second column line pair;
• first isolating means responsive to said one of said isolation timing signals for isolating said first N-sense amplifier from said first pair of column line halves during at least a portion of said second row access cycle, said first N-sense amplifier connected to said first pair of column line halves through said first isolating means;
• second isolating means responsive to one of said isolation timing signals for isolating said first N-sense amplifier from said second pair of column line halves during at least a portion of said first row access cycle, said first N-sense amplifier connected to said second pair of column line halves through said second isolating means;
• third isolating means responsive one of said isolation timing signals for isolating said second N-sense amplifier from said third pair of column line halves during at least a portion of said second row access cycle, said second N-sense amplifier connected to said third pair of column line halves through said third isolating means;
• and
• fourth isolating means responsive to one of said isolation timing signals for isolating said second N-sense amplifier from said fourth pair of column line halves during at least a portion of said first row access cycle said second N-sense amplifier connected to said fourth pair of column line halves through said fourth isolating means.