Integrated circuit memory device having flash clear
AssigneeSGS-Thomson Microelectronics S.A.
InventorBahador Rastegar
Life of this patent
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Abstract
A dual-port memory device provides bit lines having a crossover pattern to reduce stray end coupling capacitances. Such crossover occurs approximately in the middle of the memory array for the device. Data in one-half of the array is stored in an inverted manner from data in the other half of the array. A preferred technique for clearing a memory provides for resetting only a portion of the bits of the array for each entry, with the bits of all memory entries being reset simultaneously. In order to provide such a reset function with the preferred bit line crossover scheme, a voltage node used for reset must also provide signal lines which are crossed over in the middle of the array.
Claims18
A dual port memory device, comprising:
- an array of memory cells, said array divided into a first part and a second part along a line in a first direction;
- a plurality of bit lines traversing the array in a second direction perpendicular to the first direction, said bit lines being grouped into a first group corresponding to a first port and a second group corresponding to a second port, with each cell of the array being accessible by bit lines from both the first and second groups, and wherein bit lines in the first group cross over bit lines in the second group in a crossover region between the first and second memory parts;
- a first plurality of power supply lines traversing said array in the second direction;
- and
- a second plurality of power supply lines for which the voltage can be changed, said second plurality crossing over selected of said first plurality of power supply lines in the crossover region to lie adjacent a selected side of a column of cells in the second direction, wherein such column of cells can be simultaneously set to a known value by changing the voltage on said second plurality of power supply lines.
A method for writing data into a dual port memory array, comprising the steps of:
- for a first port, writing data into the array in its uncomplemented form at addressed locations;
- for the first port, reading data from the array in its uncomplemented form;
- for a second port, writing data into a first part of the array in its uncomplemented form at addressed locations, and writing data into a second part of the array in an inverted form at addressed locations;
- for the second port, reading data from the first part of the array in its uncomplemented form, and reading data from the second part of the array in its complemented form, using a single sense amplifier for both parts of the array;
- and
- for a plurality of columns of bits, simultaneously resetting all memory cells in such columns to a preselected state by changing a value of a power supply input to such cells.
A dual port memory device, comprising:
- an array of memory cells organized into rows and columns, wherein the rows are divided into first and second groups;
- a plurality of bit lines traversing the array in the column direction, wherein said bit lines cross over each other in a crossover region between the first and second row groups, a first set of bit lines associated with a first port and a second set of bit lines associated with a second port;
- means connected to the array for inverting data read from the second group of rows by the second port, and for inverting data to be written to the second group of rows through the second port, wherein data communicated to and from the array through the first port is not inverted;
- a plurality of first power supply lines traversing the array in the column direction for providing a power terminal to columns of memory cells;
- a plurality of second power supply lines traversing the array in the column direction for providing a power terminal to resettable columns of memory cells;
- and
- means for changing the voltage on said second plurality of power supply lines to simultaneously reset all of the cells in the resettable columns to a preselected value.
Dependencies are inferred from the claim text.