US 5,311,476 A · Semiconductor memory, components and layout arrangements thereof, and method of testing the memory

Abstract

There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse. With respect to the semiconductor memory, such as the pseudostatic RAM, the initial count of the refresh timer counter circuit of the refresh timer circuit can be set at an optional value by applying a signal to an address input terminal, and a test mode can be effected in which the refresh period can be set at an optional value by accordingly applying a test control signal to a predetermined external terminal. Therefore, the discharge current of the oscillation circuit capacitor associated with the refresh timer circuit becomes stabilized, noting the particular layout arrangement regarding the polycrystalline silicon layer forming the resistor of the oscillation circuit, and the fact that same parasitic capacitances are effectively connected between the polycrystalline silicon resistor and the supply voltage of the circuit and between the polycrystalline silicon resistor and the ground potential of the circuit thereby cancelling any variation of the output of the power source. Therefore, variation of the oscillation frequency of the oscillation circuit attributable to the bumping of the power source can be effectively suppressed.

Claims42

Dependent claims

An oscillation circuit comprising:

a first MOSFET the charging or discharging current of which determines the frequency of oscillation;
a second MOSFET coupled in a current-mirror relation with said first MOSFET;
resistor means, coupled in series with said second MOSFET between respective connections supplied with first and second supply voltages, substantially for setting the valve of the charging current or the discharging current;
a first logic inverter having an input coupled to an output of said first MOSFET thereby effecting a charging/discharging node;
and a series arrangement of a delay circuit and a second logic inverter coupled between an output of said first logic inverter and an output node of said oscillation circuit and being included in a feedback circuit for effecting control of said charging or discharging current,
wherein said resistor means includes a polycrystalline silicon layer formed on an insulating layer over a main surface of a semiconductor substrate of a first conductivity type, and
wherein said polycrystalline silicon layer is extended over respective first and second main surface well regions of said semiconductor substrate, said first and second wall regions being of a second conductivity type, opposite that of said first conductivity type, and said first and second well regions being biased by said first and second supply voltages, respectively.

4 more elements

An oscillation circuit, powered by first and second supply voltages, comprising:

a first capacitor provided between a first internal node of said oscillation circuit and said second supply voltage;
a level comparing circuit having an input coupled to said first internal node and having an output;
a logic inversion delay circuit which receives the output signal of said level comparing circuit;
a first MOSFET which is set to the ON state selectively according to the output signal of said logic inversion delay circuit, provided between said first supply voltage and said first internal node;
a second capacitor provided between a second internal node of said oscillation circuit and said second supply voltage;
a voltage generating circuit, operating by said first and second supply voltages, which provides a predetermined set voltage at an output node thereof;
a second MOSFET which is set to the ON state selectively according to the output signal of the inversion delay circuit and substantially simultaneously with said first MOSFET, provided between the output node of said logic said voltage generating circuit and said second internal node;
a third MOSFET having a gate coupled to said second internal node;
a series circuit including resistor means and a fourth MOSFET provided between said third MOSFET and said second supply voltage;
and a fifth MOSFET provided between said first internal node and said second supply voltage and being coupled in a current-mirror relation with said fourth MOSFET.

7 more elements

Dependencies are inferred from the claim text.

Semiconductor memory, components and layout arrangements thereof, and method of testing the memory

Life of this patent

Semiconductor memory, components and layout arrangements thereof, and method of testing the memory

Life of this patent

Abstract

Claims42