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US 5,311,472 AGranted
Redundant decoder circuit
AssigneeNEC Corporation
InventorKen Ota
Life of this patent
Estimating the term…
Abstract
A redundant decoder circuit includes a restoration circuit for restoring a decoder which activates a redundant memory cell. When the redundant memory cell which should store a predetermined information is disabled, the restoration circuit stops the decoder from supplying the active signal to the disabled memory cell. Therefore, the predetermined information is to be stored in another memory cell instead of the disabled memory cell, so that the redundant memory cell is used effectively.
Claims5
A redundant decoder circuit comprising:
- means for storing an address to designate a memory cell of a main memory which is disabled;
- means for generating a first decode signal, when an address signal coincides with said address stored in said storing means;
- a memory cell of a redundant memory for storing information, when said first decode signal is generated;
- and
- means for restoring said generating means to generate a second decode signal which is an inverted signal of said first decode signal, said restoring means being activated at a time when said memory cell of said redundant memory is disabled.
2 more elements
A redundant decoder circuit comprising:
- a first decoder circuit for generating a first decode signal in accordance with a first address signal, by which a first memory cell of a redundant memory is addressed;
- a second decoder circuit for generating a second decode signal in accordance with a second address signal, by which a second memory cell of a redundant memory is addressed;
- and
- a control circuit for addressing said second memory cell in accordance with said first decode signal, when said first memory cell is disabled.
1 more element
Dependencies are inferred from the claim text.