Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array having at least one cell array unit, said cell array unit including a plurality of memory cells;
• selection means for selecting at least one of said memory cells in accordance with an externally supplied address;
• an input/output terminal for outputting data read from said selected memory cell and for receiving data supplied externally and sending said data to said selected memory cell;
• at least one data line for connecting said input/output terminal to each said cell array unit;
• sense amplifiers serially connected to each said data line in a multiple stage configuration for amplifying said read data;
• a write buffer connected in parallel with one of said sense amplifiers connected to each said data line;
• by-pass switching means connected between input and output terminals of the other sense amplifiers connected to each said data line;
• a control circuit for applying an on-signal to at least one said by-pass switching means when writing data, said on-signal turning on said by-pass switching means;
• and
• a read/write selector, said control circuit receiving a write mode signal outputted from said read/write selector and outputting said on/signal,
• wherein said data line is a pair of complementary data lines for transferring complementary data to and from each said memory cell, and
• wherein said selection means includes a row decoder and a column decoder, respectively for receiving and decoding an address.

A semiconductor memory device comprising:

• a memory cell array having cell array units, said cell array units including a plurality of memory cells;
• selection means for selecting at least one of said memory cells in accordance with an externally supplied address, said selection means includes a row decoder and a column decoder, respectively, for receiving an decoding an address;
• an input/output terminal for outputting data read from said selected memory cell and for receiving data supplied externally and sending said data to said selected memory cell;
• at least one data line for connecting said input/output terminal to each of said cell array units;
• sense amplifiers serially connected to each said data line in a multiple stage configuration for amplifying said read data;
• a write buffer connected in parallel with one of said sense amplifiers connected to each said data line;
• by-pass switching means connected between input and output terminals of the other sense amplifiers connected to each said data line;
• a control circuit for applying an on-signal to at least one said by-pass switching means when writing data, said on-signal turning on said by-pass switching means;
• and
• a read/write selector for outputting a write mode signal to said control circuit so that said control circuit outputs said on-signal.