Selective bulk write operation

A memory in an integrated circuit, comprising:

• a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;
• a plurality of pairs of bit lines, each associated with one of the columns;
• a column decoder for selecting a plurality of columns in the array responsive to a column address;
• a plurality of word line drivers for selecting, in response to a row address, a row of memory cells wherein each memory cell is connected to its associated pair of bit lines;
• a plurality of row isolation circuits for isolating a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal, each row isolation circuit having a conduction path between the selected memory cells in the associated row and the remainder of the row;
• and
• means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal, each including a first pull-up transistor connected to a first bit line of its associated bit line pair and a second pull-up transistor connected to a second bit line of its associated bit line pair, and means, connected to a bit line of the bit line pair, for driving the bit line to a selected value in response to the bulk write signal.

A memory in an integrated circuit, comprising:

• a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;
• a plurality of pairs of bit lines, each associated with one of the columns;
• a column decoder for selecting a plurality of columns in the array responsive to a column address;
• means for isolating a selected group of memory cells in each row from the remainder of the row in response to a bulk write signal, including a pass gate having a conductive path and a control terminal for isolating the selected memory cells in each row from the remainder of the row in response to the bulk write signal, and an enable transistor for selecting, in response to the bulk write signal, the selected group of memory cells;
• and
• means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal.

A memory in an integrated circuit, comprising:

• a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;
• a plurality of pairs of bit lines, each associated with one of the columns;
• a column decoder for selecting a plurality of columns in the array responsive to a column address;
• means for isolating a selected group of memory cells in each row from the remainder of the row in response to a bulk write signal, including a pair of pass transistors, each having a conductive path and a control terminal, wherein each of the pass transistors has a conductive path between the selected group of memory cells in the row and the remainder of the memory cells in the row, and wherein a first one of the pass transistors has its control terminal connected to the bulk write signal and a second one of the pass transistors has its control terminal connected to the inverse of the bulk write signal;
• and
• means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal.

A memory in an integrated circuit, comprising:

• a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;
• a plurality of pairs of bit lines, each associated with one of the columns;
• a column decoder for selecting a plurality of columns in the array responsive to a column address;
• means for isolating a selected group of memory cells in each row and the remainder of the row in response to a bulk write signal;
• and
• means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal, such means including a first pull-up transistor connected to a first bit line of its associated bit line pair and a second pull-up transistor connected to a second bit line of its associated bit line pair, and means, connected to a bit line of the bit line pair, for driving the bit line to a selected value in response to the bulk write signal.