FLASH-EPROM with enhanced immunity from soft-programming of reference cells
AssigneeSGS-Thomson Microelectronics S.A.
InventorsVirginia Natale, Gianluca Petrosino, Flavio Scarra
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Abstract
The probability of soft-programming of the reference cells of a FLASH-EPROM memory may be excluded by having a decoupling transistor of a type of conductivity opposite to that of the cells functionally connected between the gate of each reference cell and the respective row line. Moreover the elimination of the electrical stresses to which the reference cells are subjected during the repeated programming cycles of the memory cells, increases the stability of the respective reference values of threshold and current level provided by the reference cells, thus increasing the reliability of the device.
Claims18
A FLASH-EPROM memory matrix composed of memory having families of selectable word lines and bit-lines, respectively, and comprising at least a column of individually selectable reference cells, characterized by comprising
- at least a field effect transistor of a type of conductivity opposite to the type of conductivity of the memory cells of said memory, functionally connected between a control gate of each of said reference cells and a respective word line, said transistor being capable of limiting the voltage which is applied to the control gate of a reference cell during the programming of memory cells arranged in the same row of cells of said reference cell.
In a FLASH-EPROM memory array, the improvement characterized by the presence of at least a field effect transistor of a type of conductivity opposite to the type of conductivity of the memory cells of said memory array, functionally connected between the control gate of a reference cell and a respective word-line of the memory array.
A FLASH-EPROM memory comprising a plurality of memory cells, each memory cell including a floating gate, field effect transistor of a first type of conductivity having a drain, a gate structure comprising a floating gate and a control gate, and a source, in a semiconducting substrate, organized in a matrix of rows and columns and individually addressable through at least two families of conducting lines, each line of a first family of lines connecting the control gates of the cells arranged along a same row of the matrix to a respective row selection circuitry, each line of said second family of lines connecting the drains of cells arranged along a same column of the matrix to a respective column selection circuitry, a line of said second family of lines connecting in common the drains of the cells of a column of reference cells, the sources of all the cells of the matrix being connected to a common source node which is maintained at a virtual ground potential at least during the reading of the data stored in memory;
- characterized by comprising
- at least a field effect transistor of a type of conductivity opposite to said first type of conductivity functionally connected between the control gate of each of said reference cells of said column and each respective line of said first family of lines connecting the control gates of the memory cells that are connected to the same row, respectively, to said row selection circuitry;
- said transistor having a source connected to the control gate of a respective reference cell of said column of respective reference cells, a drain connected to said respective line of the first family of lines, a gate connected to a real ground node and a body connected to a supply rail of the memory;
- said at least transistor limiting the voltage which is applied to the control gate structure of the respective reference cell of said column of reference cells during the programming of memory cells belonging in the same row.
A FLASH-EPROM memory array comprising:
- a plurality of memory cells, each of said memory cells including a drain region, a gate structure, and a source region;
- a plurality of reference cells, each reference cell having a gate;
- a word-line electrically connected to the gate structure of a plurality of the memory cells within the memory;
- a field effect transistor functionally connected between the gate of a respective reference cell and the respective word-line.
Dependencies are inferred from the claim text.