Semiconductor memory cell farming a ROM cell from a RAM cell

A semiconductor memory cell comprising:

• a word line;
• a pair of bit lines crossing the word line;
• a first resistance having a first side connected to a high power source and having a second side connected to a first connecting node;
• a second resistance having a first side connected to a high power source and having a second side connected to a second connecting node;
• a first field effect transistor (FET) connected between the first connecting node and a low power source and having a gate connected to the low power source;
• a second FET connected between the second connecting node and the low power source and having a gate connected to the low power source;
• a third FET connected between the first connecting node and one of the pair of bit lines and having a gate connected to the word line to control the operation of the third FET by changing a potential of the word line;
• and
• a fourth FET connected between the second connecting node and the other of the pair of bit lines and having a gate connected to the word line to control the operation of the fourth FET by changing the potential of the word line.

A semiconductor memory cell comprising:

• a word line;
• a pair of bit lines crossing the word line;
• a first resistance having a first side connected to a high power source and having a second side connected to a first connecting node;
• a second resistance having a first side connected to the high power source and having a second side connected to a second connecting node;
• a first field effect transistor (FET) connected between the first connecting node and a low power source and having a gate directly connected to the high power source;
• a second FET connected between the second connecting node and the lower power source and having a gate directly connected to the high power source;
• a third FET connected between the first connecting node and one of the pair of bit lines and having a gate connected to the word line to control the operation of the third FET by changing a potential of the word line;
• and
• a fourth FET connected between the second connecting node and the other of the pair of bit lines and having a gate connected to the word line to control the operation of the fourth FET by changing the potential of the word line.

A semiconductor memory cell comprising:

• a word line;
• a pair of bit lines crossing the word line;
• a resistance having a first side is connected to a high power source and a second side connected to a first connecting node;
• a first effect transistor (FET) connected between the first connecting node and a low power source and having a gate connected to a second connecting node;
• a second FET connected between the second connecting node and the low power source and having a gate connected to the first connecting node;
• a third FET connected between the first connecting node and one of the pair of bit lines and having a gate connected to the word line to control the operation of the third FET by changing a potential of the word line;
• and
• a fourth FET connected between the second connecting node and the other of the pair of bit lines and having a gate connected to the word line to control the operation of the fourth FET by changing the potential of the word line,
• wherein the first FET is a depletion type FET and the second FET is an enhancement type FET.