Technology mapping apparatus for a combination circuit for use in automatically synthesizing an LSI logic circuit

A technology mapping apparatus for automatically synthesizing an LSI logic circuit by mapping circuit elements of a combination circuit to cells which form said LSI logic circuit, comprising:

• graph converting means for converting functionally descriptive information expressing a combination circuit into a first graph expression having only NOR and inversion circuits;
• multiple input NOR converting means for detecting from the first graph expression a circuit element having a NOR circuit and an inversion circuit alternately connected in series and for converting said circuit element to a second graph expression where a multiple input NOR circuit replaces said circuit element;
• and
• means for executing technology mapping for the second graph expression obtained by said multiple input NOR converting means.

A technology mapping apparatus for automatically synthesizing an LSI logic circuit my mapping circuit elements of a combination circuit to cells which form said LSI logic circuit, comprising:

• graph converting means for converting functionally descriptive information expressing a combination circuit into a first graph expression having only NOR and inversion circuits;
• multiple input NOR converting means for detecting from the first graph expression a circuit element having a NOR circuit and an inversion circuit alternately connected in series and for converting said circuit element to a second graph expression where a multiple input NOR circuit replaces said circuit element;
• and
• cell mapping means for detecting from at least one of the first and second graph expressions a circuit element having NOR circuits connected together in series, and for mapping said circuit element to at least one of a plurality of sets of gate cells, at least some of the sets of the gate cells including a composite cell.

The technology mapping apparatus for automatically synthesizing an LSI logic circuit by mapping circuit elements of a combination circuit to cells which form said LSI logic circuit, comprising:

• graph converting means for converting functionally descriptive information expressing a combination circuit into a first graph expression having only NAND and inversion circuits;
• multiple input NAND converting means for detecting from the first graph expression a circuit element having a NAND circuit and an inversion circuit alternately connected in series and for converting said circuit element to a second graph expression where a multiple input NAND circuit replaces said circuit element;
• and
• cell mapping means for detecting from at least one of the first and second graph expressions a circuit element having NAND circuits connected together in series, for mapping said circuit element to at least one of a plurality of sets of gate cells, at least some of the sets of the gate cells including a composite cell, and for outputting a mapping result with a minimum number of gates as a mapping output for said circuit element.

The technology mapping apparatus for automatically synthesizing an LSI logic circuit by mapping circuit elements of a combination circuit to cells which form said LSI logic circuit, comprising:

• graph converting means for converting functionally descriptive information expressing a combination circuit into a first graph expression having only NAND and inversion circuits;
• multiple input NAND converting means for detecting from the first graph expression a circuit element having a NAND circuit and an inversion circuit alternatively connected in series and for converting said circuit element to a second graph expression where a multiple input NAND circuit replaces said circuit element;
• and
• means for executing technology mapping for the second graph expression obtained by said multiple input NAND converting means.

A technology mapping apparatus for automatically synthesizing an LSI logic circuit by mapping circuit elements of a combination circuit to cells which form said LSI logic circuit, comprising:

• graph converting means for converting functionally descriptive information expressing a combination circuit into a first graph expression having only NAND and inversion circuits;
• multiple input NAND converting means for detecting from the first graph expression a circuit element having a NAND circuit and an inversion circuit alternatively connected in series and for converting said circuit element to a second graph expression where a multiple input NAND circuit replaces said circuit element;
• and
• cell mapping means for detecting from at least one of the first and second graph expressions a circuit element having NAND circuits connected together in series, for mapping said circuit element to at least one of a plurality of sets of gate cells, at least some of the sets of the gate cells including a composite cell.