RF test equipment and wire bond interface circuit

An RF test equipment and wire bond interface circuit, disposed on a dielectric wafer, for facilitating the on-wafer testing of integrated circuits (ICs) formed on the dielectric wafer, prior to the IC's separation from the wafer, said interface circuit comprising:

• electrical interface means, disposed on the wafer, for providing electrical coupling between external test equipment and an IC under test;
• and
• a low pass filter structure, disposed on the wafer between the electrical interface means and the IC under test, for providing simulated wire bond reactance, said low pass filter structure comprising:
• a first inductive element connected in series with the electrical interface means for simulating said wire bond reactance,
• a second inductive element connected in series with the first inductive element for making contact with the IC under test, and
• at least one capacitor connected between ground and a point common to both the first and the second inductive elements for providing shunt capacitance,
• such that when the external test equipment makes contact with the electrical interface means, RF testing with simulated wire bond reactance is provided, thereby assuring similar on-wafer and off-wafer performance of the IC.

An RF test equipment and wire bond interface circuit, disposed on a dielectric wafer, for facilitating the on-wafer testing of integrated circuits (IC) formed on said dielectric wafer, said RF test equipment and wire bond interface circuit comprising:

• an electrical interface means, disposed on a surface of the dielectric wafer, for providing electrical coupling between external test equipment and an IC under test;
• and
• a matching circuit, disposed on a surface of the wafer, between the electrical interface means and the IC under test, for providing impedance matching and simulated wire bond reactances, said matching circuit comprising:
• a first inductive element, connected in series with the electrical interface means, for simulating said wire bond reactances,
• a second inductive element, connected in series with the first inductive element, for making contact with the IC under test, and
• at least one electrical wire bond contact, coupled between ground and a point common to both the first and the second inductive elements, for providing wire bond contact and shunt capacitance,
• such that when the external test equipment makes contact with the electrical interface means, a low-pass filter structure which simulates wire bond reactance is provided during RF testing.

An RF test equipment and wire bond interface circuit, disposed on a substrate, for facilitating the on-substrate testing of integrated circuits (IC) formed on the substrate, said circuit comprising:

• an electrical interface means, disposed on a surface of the substrate, for providing electrical coupling between external test equipment and an IC under test;
• and
• a matching circuit, disposed on a surface of the substrate between the electrical interface means and the IC under test, for providing impedance matching and simulated wire bond reactance, said matching circuit comprising:
• a first inductive element, connected in series with the electrical interface means, for simulating wire bond reactances,
• a second inductive element, connected in series with the first inductive element, for making contact with the IC under test, and
• an electrical wire bond contact, coupled between ground and a point common to both the first and the second inductive elements, for providing shunt capacitance and wire bond contact to external circuitry,
• such that when the external test equipment makes contact with the electrical interface means, a low-pass filter structure having a first transfer characteristic is provided during RF testing, further;
• when the IC under test is removed from the substrate and wire bonds are attached between the electrical wire bond contact and external circuitry, a low-pass filter structure having a second transfer characteristic is provided during IC packaging, wherein said second transfer characteristic is substantially similar to the first transfer characteristic, thereby assuring similar on-wafer and off-wafer performance of the IC.