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US 5,311,086 AGranted
Multiplying circuit with improved linearity and reduced leakage
AssigneeKabushiki Kaisha Toshiba
InventorsTakafumi Yamaji, Chikau Yakahashi, Hiroshi Tanimoto
Life of this patent
Estimating the term…
Abstract
A multiplying circuit in which a pair of common-base transistors each having a small emitter area are inserted between the common emitter terminals of first and second differential amplifiers, which amplify a signal input to an input terminal pair and are connected in such a way as to cancel out their outputs which correspond to the input signal, and the output terminal pairs of multiple third differential amplifiers, which amplify a signal input to another input terminal pair and have a predetermined DC offset characteristic.
Claims21
A multiplying circuit comprising:
- first and second differential amplifiers for receiving a first input signal and each having first and second output terminals and a common emitter terminal, the first output terminal of said first differential amplifier being connected to the second output terminal of said second differential amplifier, and the second output terminal of said first differential amplifier being connected to the first output terminal of said second differential amplifier;
- load means connected to said first and second output terminals of said first and second differential amplifiers;
- first and second common-base transistors having bases tied to a constant potential and collectors respectively connected to said common emitter terminals of said first and second differential amplifiers;
- and
- a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a predetermined DC offset and third and fourth output terminals, and said emitters of said first and second common-base transistors being connected only to said third and fourth output terminals of said third differential amplifiers, respectively, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.
2 more elements
A multiplying circuit comprising:
- a plurality of first differential amplifiers and a plurality of second differential amplifiers for receiving a first input signal, each of said first and second differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, the first output terminal of each of said first differential amplifiers being connected to the second output terminal of one of said second differential amplifiers, and the second output terminal of each of said first differential amplifiers being connected to the first output terminal of one of said second differential amplifiers;
- load means connected to said first and second output terminals of said first and second differential amplifiers;
- a plurality of first common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said first differential amplifiers, and emitters commonly connected;
- a plurality of second common-base transistors having bases also tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said second differential amplifiers, and emitters commonly connected;
- and
- a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a predetermined DC offset and third and fourth output terminals and said common emitter terminals of said first and second common-base transistors being connected only to the third and fourth output terminals of each of said third differential amplifiers, respectively, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.
3 more elements
A multiplying circuit comprising:
- a plurality of first differential amplifiers and a plurality of second differential amplifiers for receiving a first input signal, each of said first and second differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, the first output terminal of each of said first differential amplifiers being connected to the second output terminal of one of said second differential amplifiers, and the second output terminal of each of said first differential amplifiers being connected to the first output terminal of one of said second differential amplifiers;
- load means connected to said first and second output terminals of said first and second differential amplifiers;
- a plurality of first common-base transistors having bases tied to a constant potential, collectors connected to said common emitter terminals of said first differential amplifiers, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have a predetermined emitter area ratio;
- a plurality of second common-base transistors, having bases tied to a constant potential, collectors connected to said common emitter terminals of said second differential amplifiers, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have a predetermined emitter area ratio;
- and
- a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a pair of output terminals, said common emitter terminals of said first and second common-base transistors being connected only to respective output terminals of each of said third differential amplifiers, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.
3 more elements
A multiplying circuit comprising:
- a plurality of first differential amplifiers and a plurality of second differential amplifiers for receiving a first input signal, each of said first and second differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal, the first output terminal of each of said first differential amplifiers being connected to the second output terminal of one of said second differential amplifiers, and the second output terminal of each of said first differential amplifiers being connected to the first output terminal of one of said second differential amplifiers;
- load means connected to said first and second output terminals of said first and second differential amplifiers;
- a plurality of first common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said first differential amplifiers, and emitters;
- a plurality of second common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said second differential amplifiers, and emitters;
- a plurality of third common-base transistors having bases tied to a constant potential, collectors connected to emitters of said first common-base transistors, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have a predetermined emitter area ratio;
- a plurality of fourth common-base transistors having bases tied to a constant potential, collectors connected to emitters of said second common-base transistors, respectively, and emitters commonly connected to obtain a common emitter terminal, said emitters being set to have the predetermined emitter area ratio;
- and
- a plurality of third differential amplifiers for receiving a second input signal, each of said third differential amplifiers having a pair of output terminals, said common emitter terminals of said third and fourth common-base transistors being connected only to respective output terminals of each of said third differential amplifiers, whereby an output signal proportional to the product of the first and second input signals appears between the first and second output terminals of said first and second differential amplifiers.
5 more elements
A multiplying circuit comprising:
- a differential amplifier for receiving a first input signal, having first and second output terminals and a common emitter terminal;
- a load circuit connected to at least one of said first and second output terminals of said differential amplifier;
- a common-emitter transistor having a base supplied with a second input signal;
- and
- a common-base transistor having a base tied to a constant potential, a collector connected only to said common emitter terminal of said differential amplifier, and an emitter connected only to a collector of said common-emitter transistor and having a smaller emitter area than said common-emitter transistor whereby an output signal proportional to the product of the first and second input signals appears at at least one of the first and second output terminals of said differential amplifier.
2 more elements
A multiplying circuit comprising:
- a plurality of differential amplifiers for receiving a first input signal, each of said differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal,
- a load circuit connected to at least one of said first and second output terminals of each of said differential amplifiers;
- a common-emitter transistor having a base supplied with a second input signal and
- a plurality of common-base transistors having bases tied to a constant potential, collectors each connected only to a respective one of said common emitter terminals of said multiple differential amplifiers, respectively, and emitters connected only to a collector of said common-emitter transistor, said emitters of said common-base transistors being set to have a predetermined emitter area ratio.
1 more element
A multiplying circuit comprising:
- a plurality of differential amplifiers for receiving a first input signal, each of said differential amplifiers having a predetermined DC offset and first and second output terminals and a common emitter terminal,
- a load circuit connected to at least one output terminal of said first and second output terminals of each of said differential amplifiers;
- a common-emitter transistor having a base supplied with a second input signal;
- a plurality of first common-base transistors having bases tied to a constant potential, and emitters connected only to a collector of said common-emitter transistor, the emitters of said first common-base transistors being set to have a predetermined emitter area ratio;
- and
- a plurality of second common-base transistors having bases tied to a constant potential different from the constant potential applied to said first common-base transistors, collectors respectively connected to said common emitter terminals of said multiple differential amplifiers and emitters respectively connected to collectors of said first common-emitter transistors and having emitter areas equal to or smaller than a minimum emitter area of one of said first common-base transistors.
3 more elements
A multiplying circuit apparatus comprising:
- a plurality of multiplying circuits to which a plurality of first input signals are supplied respectively;
- and
- a common-emitter transistor commonly connected to said plurality of multiplying circuits and having a base to which a second input signal is supplied,
- each of said plurality of multiplying circuits comprising:
- a differential amplifier for receiving one of said first input signals, having first and second output terminals and a common emitter terminal;
- load means connected to said first and second output terminals;
- and
- a common-base transistor having a base tied to a constant potential and a collector connected only to said common emitter terminal of said differential amplifier,
- whereby an output signal proportional to the product of the first and second input signals is obtained from said multiplying circuits.
6 more elements
Dependencies are inferred from the claim text.