US 5,311,085 AGranted

Clocked comparator with offset-voltage compensation

AssigneeU.S. Philips Corporation

InventorsMarcellinus J. M. Pelgrom, Antonia C. Van Rens

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Abstract

A clocked comparator circuit comprises an input stage and a sample-and-hold circuit and an amplifier-latch circuit coupled to the output of the input stage. The sample-and-hold circuit provides an accurate offset-voltage compensation and the amplifier-latch circuit provides a high operating speed by means of a switchable current source (S6, T11). Switches are provided so that the amplifier-latch circuit constitutes a differential load having a high positive impedance during a first state of a clock signal, a low positive impedance during a next state of the clock signal, and a negative impedance during a following state of the clock signal.

Claims17

Dependent claims

A comparator circuit for converting a voltage difference appearing between a first and a second input terminal of the comparator circuit during a first state of a clock signal into a voltage difference appearing between a first and a second output terminal during a second state of the clock signal, the comparator circuit comprising:

an input differential amplifier having a non-inverting input and an inverting input and having an inverting output and a non-inverting output coupled respectively to the first and the second output terminal of the comparator circuit, first switching means for coupling a voltage difference appearing between the first and the second input terminal during the first state of the clock signal to the non-inverting input and the inverting input respectively, a sample-and-hold circuit coupled to the inverting output and the non-inverting output of the input differential amplifier and comprising a further differential amplifier having a first input coupled to a first capacitor and a second input coupled to a second capacitor, and means coupling an amplifier-latch circuit to the inverting output and the non-inverting output of the input differential amplifier, the amplifier-latch circuit comprising a first pair of diode-connected transistors coupled between a first common node and the inverting output and the non-inverting output of the input differential amplifier, a second pair of cross-coupled transistors coupled between a second common node and the inverting output and the non-inverting output of the input differential amplifier, a current-mirror with a switchable current transfer having an input terminal coupled to the second common node and an output terminal, and further switching means for coupling the output terminal of the current-mirror to the first common node during the first and a third state of the clock signal and for switching the current transfer of the current mirror from a first transfer value to a second transfer value during at least the third state of the clock signal, wherein the third state of the clock signal occurs between the first and second clock signal states.

A clocked comparator circuit for converting an input voltage at a first and a second input terminal during a first state of a clock signal into an output voltage appearing between a first and a second output terminal of the comparator circuit during a second state of the clock signal, the comparator circuit comprising:

an input differential amplifier having a first input and a second input and having a first output and a second output coupled respectively to the first and the second output terminal of the comparator circuit, first switching means for coupling an input voltage appearing between the first and the second input terminal to the first and second input, respectively, of the input differential amplifier during the first state of the clock signal, a sample-and-hold circuit comprising a further differential amplifier having a first input coupled to a first capacitor and a second input coupled to a second capacitor and second and third switching means for coupling said first and second input of the further differential amplifier to the first and second outputs of the input differential amplifier during the first state of the clock signal, and an amplifier-latch circuit coupled to the first and second outputs of the input differential amplifier, and wherein the amplifier-latch circuit comprises two diode-connected transistors coupled to a current source via fourth switching means and to a further current source via fifth switching means.

A comparator circuit for converting, during a first state of a clock signal, an input voltage at a first and a second input terminal into an output voltage appearing between a first and a second output terminal of the comparator circuit during a second state of the clock signal, the comparator circuit comprising:

an input differential amplifier having a first input and a second input and having a first output and a second output coupled respectively to the first and the second output terminal of the comparator circuit,
first switching means for coupling an input voltage appearing between the first and the second input terminal to the first and second input, respectively, of the input differential amplifier,
a sample-and-hold circuit comprising a further differential amplifier coupled to first and second capacitors,
an amplifier-latch circuit coupled to the first and second outputs of the input differential amplifier to form a load, and
further switching means controlled by the clock signal so that the amplifier-latch circuit constitutes a load having a high positive impedance during the first state of the clock signal, a negative impedance during the second state of the clock signal, and a low positive impedance during a third state of the clock signal that occurs between the first and second states of the clock signal.

2 more elements

Dependencies are inferred from the claim text.

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Abstract

an input differential amplifier having a non-inverting input and an inverting input and having an inverting output and a non-inverting output coupled respectively to the first and the second output terminal of the comparator circuit, first switching means for coupling a voltage difference appearing between the first and the second input terminal during the first state of the clock signal to the non-inverting input and the inverting input respectively, a sample-and-hold circuit coupled to the inverting output and the non-inverting output of the input differential amplifier and comprising a further differential amplifier having a first input coupled to a first capacitor and a second input coupled to a second capacitor, and means coupling an amplifier-latch circuit to the inverting output and the non-inverting output of the input differential amplifier, the amplifier-latch circuit comprising a first pair of diode-connected transistors coupled between a first common node and the inverting output and the non-inverting output of the input differential amplifier, a second pair of cross-coupled transistors coupled between a second common node and the inverting output and the non-inverting output of the input differential amplifier, a current-mirror with a switchable current transfer having an input terminal coupled to the second common node and an output terminal, and further switching means for coupling the output terminal of the current-mirror to the first common node during the first and a third state of the clock signal and for switching the current transfer of the current mirror from a first transfer value to a second transfer value during at least the third state of the clock signal, wherein the third state of the clock signal occurs between the first and second clock signal states.