US 5,311,083 A · Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads

Abstract

A CMOS integrated circuit (IC) device embodiment of the present invention comprises an internal logic circuit operating with traditional 3.3 volt or five volt internal logic levels, an output buffer to convert the internal logic levels to external logic levels of 0.3 volts and an input buffer to convert the 0.3 volt external logic levels to the internal logic levels. In a CMOS IC device having numerous external output loads including relatively high capacitive values that are driven at very high clock rates, the restricted voltage swings of the 0.3 volt external logic levels permit unusually large numbers of devices to be driven without exceeding a predetermined power dissipation limit of the CMOS IC device. The low external logic levels further permit electrostatic discharge (ESD) protection to be included on all signal inputs and outputs of the CMOS IC device. The ESD protection comprises a pair of opposite polarity silicon PN junction diodes in parallel and connected between each signal line and a ground reference.

Claims20

Dependent claims

A system including a plurality of inter-connected packaged CMOS devices, each device comprising:

input buffer means for receiving logic levels not exceeding 0.5 volts and for interfacing to an internal logic circuit operating with logic levels exceeding 3.3 volts;
and
output buffer means for externally transmitting logic levels not exceeding 0.5 volts and responsive to said internal logic circuit wherein system and device power operating levels are thereby limited during high-speed and high load capacitance operation.

A CMOS integrated circuit device, with a limited power dissipation capability, for driving a relatively large plurality of external high capacitance loads at substantially high logic switching rates, the device comprising:

internal logic functional means for operating with internal logic signal levels substantially within the range of 3.3 to five volts and producing a relatively large plurality of signals for independent parallel communication to a plurality of external devices across respective relatively large capacitive loads;
and
a plurality of independent output buffer means for translating said internal logic signals to external logic levels not exceeding the forward bias voltage of a semiconductor junction diode, wherein the power dissipation when all of the plurality of independent output buffer means are driving said relatively large plurality of external high capacitance loads at a predetermined maximum switching rate is less than said limited power dissipation capability for the device.

internal logic functional means for operating with internal logic signal levels substantially within the range of 3.3 to five volts and producing a relatively large plurality of signals for independent parallel communication to a plurality of external devices across respective relatively large capacitive loads;
a plurality of independent output buffer means for translating said internal logic signals to external logic levels not exceeding the forward bias voltage of a semiconductor junction diode, wherein the power dissipation when all of the plurality of independent output buffer means are driving said relatively large plurality of external high capacitance loads at a predetermined maximum switching rate is less than said limited power dissipation capability for the device;
input buffer means for receiving logic levels not exceeding 0.5 volts and for intefacing to the internal logic functional means;
and
reference generating means for providing a voltage V.sub.IO not exceeding 0.5 volts to the input and output buffer means such that a signal output from the output buffer may operate between ground reference and V.sub.IO, and such that the input buffer means may exhibit an input threshold of approximately one-half of voltage V.sub.IO.

2 more elements

Dependencies are inferred from the claim text.

Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads

Life of this patent

Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads

Life of this patent

Abstract

Claims20