CMOS to ECL level translator

A level translator comprising:

• first and second CMOS power buses;
• a CMOS signal input;
• a CMOS buffer connected to said CMOS power buses and said CMOS signal input and comprising a PMOS transistor having a gate connected to said CMOS input, a source connected to said first CMOS power bus, and a drain;
• and an NMOS transistor having a gate connected to said CMOS input, a source connected to said second CMOS power bus, and a drain;
• an ECL power bus;
• an ECL signal output;
• an NPN bipolar transistor having a base connected to the drains of said PMOS and NMOS transistors, a collector connected to said ECL power bus, and an emitter connected to said ECL signal output;
• a second ECL power bus;
• a terminal for receiving a reference potential;
• a second bipolar transistor having a collector to the emitter of said first bipolar transistor, a base connected to said reference potential terminal, and an emitter;
• a resistor, the emitter of said second bipolar transistor being connected to said second ECL power bus through said resistor;
• and
• first and second diodes, an anode of said first diode being connected to said first-mentioned ECL power bus, a cathode of said first diode being connected to an anode of said second diode, and a cathode of said second diode being connected to said ECL signal output.

A level translator, comprising:

• first and second CMOS power buses;
• a CMOS signal input;
• a CMOS buffer connected to said CMOS power buses and said CMOS signal input;
• an ECL power bus;
• an ECL signal output;
• a bipolar transistor having a collector connected to said ECL power bus, an emitter connected to said ECL output, and a base;
• and
• a switching circuit having an input coupled to an output of said CMOS buffer and responsive to a CMOS logic level on said CMOS signal input for isolating the base of said bipolar transistor from said ECL power bus and connecting the emitter of said bipolar transistor to the base of said bipolar transistor upon the occurrence of a first CMOS logic level on said CMOS signal input, and for connecting the base of said bipolar transistor to said ECL power bus and isolating the emitter of said bipolar transistor from the base of said bipolar transistor upon the occurrence of a second CMOS logic level on said CMOS signal input.

A circuit for translating a CMOS logic level to an ECL logic level, comprising:

• means for receiving said CMOS logic level;
• means for supplying an ECL potential;
• means for furnishing an ECL logic level;
• a bipolar transistor having a collector connected to said ECL potential supplying means, an emitter connected to said ECL logic level means, and a base;
• and
• means responsive to said CMOS logic level for isolating the base of said bipolar transistor from said ECL potential and connecting the emitter of said bipolar transistor to the base of said bipolar transistor upon the occurrence of a first CMOS logic level, and for connecting the base of said bipolar transistor to said ECL potential and isolating the emitter of said bipolar transistor from the base of said bipolar transistor upon the occurrence of a second CMOS logic level.

A CMOS to ECL level translator circuit, comprising:

• a CMOS input terminal;
• a first PMOS transistor having a source connected to V.sub.DD and a drain connected to a common node;
• a first NMOS transistor having a source connected to V.sub.SS and a drain connected to said common node;
• an ECL output terminal;
• an NPN transistor having a base, a collector connected to V.sub.CC, and an emitter connected to said ECL output terminal;
• a second PMOS transistor having a source connected to V.sub.CC, a drain connected to the base of said NPN transistor, and a gate connected to said common node;
• and
• a third PMOS transistor having a source connected to the base of said NPN transistor, a drain connected to the emitter of said NPN transistor, and a gate connected to said CMOS input terminal.