Field programmable gate array with direct input/output connection
AssigneeAT&T Bell Laboratories
InventorsBarry K. Britton, Dwight D. Hill, William A. Oswald
Life of this patent
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Abstract
A field programmable gate array that includes a dedicated path that directly connects an I/O pad to a selected register in the array of programmable function units. For example, a direct connection (i.e., without a configurable interconnect point) is provided from an I/O pad, through an input driver, to the input of a selected register in a given PFU. Either this same path, or alternatively a different path, may be used to directly connect a register output from a given PFU to an I/O pad, through an output driver. This technique avoids the need for special I/O registers in the programmable input/output cells, thereby increasing the flexibility of use and ease of design of the FPGA.
Claims19
An integrated circuit comprising a field programmable gate array having:
- a multiplicity of programmable logic cells comprising at least one programmable function unit comprising at least one logic element selected from the group consisting of combinatorial logic and sequential logic, and further comprising the associated routing resources, including routing conductors and configurable interconnect points;
- and
- a multiplicity of programmable input/output cells comprising at least one driver selected from the group consisting of input driver and output driver, and further comprising one or more associated bondpads;
- characterized in that said field programmable gate array further comprises a direct path between an input, or alternatively an output, of a given logic element in a given programmable function unit, and the input driver, or alternatively the output driver, respectively, in a given programmable input/output cell.
An integrated circuit comprising a field programmable gate array having:
- a multiplicity of programmable logic cells comprising at least one programmable function unit comprising at least one look-up table and at least one register, and further comprising the associated routing resources, including routing conductors and configurable interconnect points;
- and
- a multiplicity of programmable input/output cells comprising at least one output driver and associated bondpad;
- characterized in that said field programmable gate array further comprises a direct path between the output of a register in a given programmable function unit and an output driver in a given programmable input/output cell, and
- wherein said direct path includes a multiplexer for selectively providing a signal from at least one alternative path to said output driver.
An integrated circuit comprising a field programmable gate array having:
- a multiplicity of programmable logic cells comprising at least one programmable function unit comprising at least one look-up table and at least one register, and further comprising the associated routing resources, including routing conductors and configurable interconnect points;
- and
- a multiplicity of programmable input/output cells comprising at least one input driver and associated bondpad;
- characterized in that said field programmable gate array further comprises a direct path between said input driver in a given programmable input/output cell and the input of said register in a given programmable function unit, and
- wherein said direct path includes a multiplexer for selectively providing a signal from at least one alternative path to said register.
Dependencies are inferred from the claim text.