Logic circuit and semiconductor device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiroshi Makino, Yasunobu Nakase, Kimio Ueda
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiroshi Makino, Yasunobu Nakase, Kimio Ueda
Estimating the term…
In order to obtain a logic circuit capable of performing a high-speed operation, respective gates of a P-channel MOSFET (1) and an N-channel MOSFET (2) are connected to an input node (6) in common, and ends of resistors (12, 13) are connected to respective drains thereof. Respective emitters of an NPN transistor (3) and a PNP transistor (4) are connected to an output node (9) with an end of a resistor (5) in common, and ends of the resistors (12, 13) are connected to respective bases thereof. A source of the P-channel MOSFET (1) and a collector of the NPN transistor (3) are connected to a high potential point (8) in common while a source of the N-channel MOSFET (2) and a collector of the PNP transistor (4) are connected to a low potential point (40) in common respectively. Respective other ends of the resistors (5, 12, 13) are connected at a node (7) in common. Thus, the potential of an output terminal quickly fluctuates when a bipolar transistor is in an ON state.
A logic circuit comprising:
A semiconductor device comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.