Tristate data output buffer having reduced switching noise and intermediate-level setting

A data output buffer suitable for use in a semiconductor memory device having circuitry for generating an output enable signal and an inverse output enable signal, comprising:

• a data output node;
• a first input circuit having a first input coupled to a first data signal, and a second input coupled to a second input circuit having a first input coupled to a second data signal, wherein said second data signal is the inverse of said first data signal, and a second input coupled to said output enable signal;
• a pull-up circuit connected to said data output node and adapted to pull up said data output node to a high voltage level in response to the output of said first input circuit going from a first logic state to a second logic state;
• a pull-down circuit connected to said data output node and adapted to pull down said data output node to a low voltage level in response to the output of said second input circuit going from a first logic state to a second logic state;
• a preset circuit comprising:
• a pull-up stage comprised of a first MOS transistor having a first electrode connected to a high voltage source, a second electrode, and a gate, and a second MOS transistor having a first electrode connected to said second electrode of said first MOS transistor, a second electrode connected to said data output node, and a gate;
• a first control circuit having a first input coupled to said output of said first input circuit, a second input coupled to said inverse output enable signal, and an output coupled to said gate of said first MOS transistor of said pull-up stage;
• a second control circuit having an input coupled to said data output node and an output connected to said gate of said second MOS transistor of said pull-up stage;
• a pull-down stage comprised of a first MOS transistor having a first electrode connected to said data output node, a second electrode, and a gate, and a second MOS transistor having a first electrode connected to said second electrode of said first MOS transistor, a second electrode connected to a low voltage source, and a gate;
• a third control circuit having an input coupled to said data output node and an output coupled to said gate of said first MOS transistor of said pull-down stage;
• a fourth control circuit having a first input coupled to said inverse output enable signal, a second input coupled to said output of said second input circuit, and an output coupled to said gate of said second MOS transistor of said pull-down stage;
• wherein said first control circuit of said preset circuit is responsive to said inverse output enable signal and said output of said first input circuit to selectively turn on said first MOS transistor of said pull-up stage;
• wherein said second control circuit of said preset circuit is responsive to a low voltage level of said data output node to selectively turn on said second MOS transistor of said pullup stage, to thereby raise the voltage level of said data output node from said low voltage level to an intermediate voltage level, during times when said first MOS transistor of said pull-up stage is turned on;
• wherein said third control circuit of said preset circuit is responsive to a high voltage level of said data output node to selectively turn on said first MOS transistor of said pulldown stage, to thereby lower the voltage level of said data output node from a high voltage level to said intermediate voltage level, during times when said second MOS transistor of said pull-down stage is turned on;
• wherein said fourth control circuit of said preset circuit is responsive to said output signal of said second input circuit and said inverse output enable signal for selectively turning on said second MOS transistor of said pull-down stage;
• and,
• wherein said intermediate voltage level is higher than said low voltage level but less than said high voltage level.