Seu-immune latch for gate array, standard cell, and other asic applications

A latch circuit comprising:

• first and second complementary channel transistor inverters having respective input and output nodes thereof cross-coupled to one another;
• first and second pairs of decoupling transistors respectively coupled in circuit paths containing the output nodes of said first and second complementary channel transistor inverters and first and second voltage supply terminals;
• and
• third and fourth complementary channel transistor inverters having respective input and output nodes thereof cross-coupled to one another and to the gates of respective ones of said first and second pairs of complementary channel decoupling transistors and third and fourth pairs of complementary channel decoupling transistors respectively coupled in circuit with output nodes of said third and fourth complementary channel transistor inverters and said first and second voltage supply terminals, and wherein the cross-coupled input and output nodes of said first and second complementary channel transistor inverters are coupled to the gates of selected ones of said third and fourth pairs of complementary channel decoupling transistors.

A latch circuit comprising:

• a first latch comprising first and second complementary channel transistor inverters having respective input and output nodes thereof cross-coupled to one another, and first and second pairs of decoupling transistors respectively coupled in circuit paths containing the output nodes of said first and second complementary channel transistor inverters and first and second voltage supply terminals;
• and
• a second latch comprising third and fourth complementary channel transistor inverters having respective input and output nodes thereof cross-coupled to one another, and third and fourth pairs of decoupling transistors respectively coupled in circuit paths containing said third and fourth complementary channel transistor inverters and said first and second voltage supply terminals;
• and
• wherein respective input nodes of said first and second latches are selectively coupled with gates of the pairs of decoupling transistors of said second and first latches.

A single event upset immune latch circuit comprising:

• a first inverter formed of a first complementary channel transistor pair having a first input node coupled to commonly connected gates thereof and a first output node coupled to commonly connected drains thereof, a second inverter formed of a second complementary channel transistor pair having a second input node coupled to commonly connected gates thereof and a second output node coupled to commonly connected drains thereof, and wherein said first input node is coupled to said second output node and said second input node is coupled to said first output node, a first pair of decoupling transistors respectively connected in circuit with source-drain paths of said first complementary channel transistor pair and first and second voltage supply terminals, and a second pair of decoupling transistors respectively connected in circuit with source-drain paths of said second complementary channel transistor pair and said first and second voltage supply terminals, and wherein first and second complementary channel transistor inverters have respective input and output nodes thereof cross-coupled to one another;
• and
• first and second pairs of decoupling transistors respectively coupled in circuit paths containing the output nodes of said first and second complementary channel transistor inverters and first and second voltage supply terminals;
• and
• wherein decoupling transistors of said first pair of decoupling transistors have control electrodes thereof connected to a first common control node, and decoupling transistors of said second pair of decoupling transistors have control electrodes thereof connected to a second common control node.

A single event upset immune latch circuit comprising:

• a first inverter formed of a first complementary channel transistor pair having a first input node coupled to commonly connected gates thereof and a first output node coupled to commonly connected drains thereof, a second inverter formed of a second complementary channel transistor pair having a second input node coupled to commonly connected gates thereof and a second output node coupled to commonly connected drains thereof, and wherein said first input node is coupled to said second output node and said second input node is coupled to said first output node, a first pair of decoupling transistors respectively connected in circuit with source-drain paths of said first complementary channel transistor pair and first and second voltage supply terminals, and a second pair of decoupling transistors respectively connected in circuit with source-drain paths of said second complementary channel transistor pair and said first and second voltage supply terminals, and wherein first and second complementary channel transistor inverters have respective input and output nodes thereof cross-coupled to one another;
• and
• first and second pairs of decoupling transistors respectively coupled in circuit paths containing the output nodes of said first and second complementary channel transistor inverters and first and second voltage supply terminals;
• and
• wherein decoupling transistors of said first pair of decoupling transistors have control electrodes thereof coupled together, and decoupling transistors of said second pair of decoupling transistors have control electrodes thereof coupled together,
• further including a third inverter formed of a third complementary channel transistor pair having a third input node coupled to commonly connected gates thereof and a third output node coupled to commonly connected drains thereof, a fourth inverter formed of a second complementary channel transistor pair having a fourth input node coupled to commonly connected gates thereof and a fourth output node coupled to commonly connected drains thereof, and wherein said third input node is coupled to said fourth output node and said fourth input node is coupled to said third output node, a third pair of decoupling transistors respectively connected in circuit with source-drain paths of said third complementary channel transistor pair and said first and second voltage supply terminals, and a fourth pair of decoupling transistors respectively connected in circuit with source-drain paths of said fourth complementary channel transistor pair and said first and second voltage supply terminals, and wherein decoupling transistors of said third pair of decoupling transistors have control electrodes thereof coupled together and decoupling transistors of said fourth pair of decoupling transistors have control electrodes thereof coupled together.

A method of imparting single event upset immunity to a latch circuit that comprises a first inverter formed of a first complementary channel transistor pair having a first input node coupled to commonly connected gates thereof and a first output node coupled to commonly connected drains thereof, a second inverter formed of a second complementary channel transistor pair having a second input node coupled to commonly connected gates thereof and a second output node coupled to commonly connected drains thereof, and wherein said first input node is coupled to said second output node and said second input node is coupled to said first output node, said method comprising the steps of:

• (a) connecting a first pair of decoupling transistors respectively in circuit between source-drain paths of said first complementary channel transistor pair and first and second voltage supply terminals, such that decoupling transistors of said first pair of decoupling transistors have control electrodes thereof connected to a first common control node;
• and
• (b) connecting a second pair of decoupling transistors respectively in circuit between source-drain paths of said second complementary channel transistor pair and said first and second voltage supply terminals, such that decoupling transistors of said second pair of decoupling transistors have control electrodes thereof connected to a second common control node.