Process for producing an arsenic-doped smooth polycrystalline silicon layer for very large scale integrated circuits

Abstract

In a multistage process for producing a smooth polycrystalline silicon layer, in particular a layer with low arsenic doping, for very large scale integrated circuits, by thermal decomposition of gaseous compounds containing the elements, a doped layer and an undoped silicon layer above the doped layer are deposited directly one after the other in a two-stage process. Initially, a surface-covering arsenic layer being at most a few atoms thick, is deposited as a preliminary lining. Then an undoped amorphous silicon layer is deposited on the arsenic layer at a temperature of less than 580.degree. C. Subsequently, the silicon layer is uniformly doped with the arsenic layer serving as a diffusion source, by temperature treatment. Simultaneously, the amorphous silicon is made into a polycrystalline silicon layer.

Dependencies are inferred from the claim text.