Back to results
US 5,309,568 AGranted
Local bus design
AssigneeOPTi Inc.
InventorsSubir Ghosh, Fong-Lu Lin
Life of this patent
Estimating the term…
Abstract
In an IBM PC AT-compatible computer architecture, CPU-generated addresses and data for accesses to a peripheral device in the I/O address space are coupled directly to the peripheral device from the local bus, without traversing the I/O bus. Any data returned from the peripheral device is coupled directly to the local bus, also without traversing the I/O bus. No buffers are needed for communicating such address and data information between the peripheral device and the I/O bus.
Claims23
Computer apparatus for use with a local device (116) having address (CA, BE#), data (CD) and control (M/IO#, W/R#, ADS#) lines, and having a local bus clock signal line carrying a local bus clock signal (CLK), said local device (116) being able to initiate a local device memory address space read access cycle to a first desired address in a memory address space by placing said first address on said address lines and issuing a first predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK), said local device (116) also being able to initiate a local device I/O address space read access cycle to a second desired address in an I/O address space distinct from said memory address space, by placing said second address on said address lines and issuing a second predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK),
- for use further with a peripheral subsystem (12) receiving control signals and having peripheral subsystem port leads (DC(15:0)) carrying data, said control signals received by said peripheral subsystem (12) including a peripheral subsystem memory address space read request signal (ADMR#) and a peripheral subsystem I/O address space read request signal (CIOR#), each of said peripheral subsystem read request signals (ADMR#, CIOR#) being received by said peripheral subsystem (12) in conjunction with a respective address received by said peripheral subsystem (12), said peripheral subsystem (12) outputting data over said peripheral subsystem port leads (DB(15:0)) in response to said peripheral subsystem memory address space read request signal (ADMR#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem memory address space read request signal (ADMR#) is within a first predefined set of addresses (A0000-BFFFF) in said memory address space, and said peripheral subsystem (12) also outputting data over said peripheral subsystem port leads (DB(15:0)) in response to said peripheral subsystem I/O address space read request signal (CIOR#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem I/O address space read request signal (CIOR#) is within a second predefined set of addresses (3BO-3DE) in said I/O address space,
- for use further with an I/O bus carrying data and control signals, said I/O bus carrying an I/O bus clock signal (BCLK) having a maximum frequency which is slower than that of said local bus clock signal (CLK), said I/O bus control signals including an I/O bus memory address space read request signal (MEMR#) which when asserted indicates a read access to an address in said memory address space, said I/O bus control signals further including an I/O bus I/O address space read request signal (IOR#) which when asserted indicates a read access to an address in said I/O address space,
- said apparatus comprising:
- a first data path (114;
- 110) which only when enabled couples any of said data on said I/O bus to said data lines of said local device (116);
- a second data path (144, 146, 148, 150;
- 110) which only when enabled couples said peripheral subsystem port leads (DB(15:0)) to said data lines of said local device (116);
- bus interface control circuitry (114) which asserts said I/O bus memory address space read request signal (MEM#) synchronously with said I/O bus clock signal (BCLK) and enables said first data path (114;
- 110), both in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF), said first data path (114;
- 110) not being enabled in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF),
- said bus interface control circuitry (114) further asserting said I/O bus I/O address space read request signal (IOR#) synchronously with said I/O bus clock signal (BCLK) and enabling said first data path (114;
- 110), both in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3B0-3DE), said first data path (114;
- 110) not being enabled in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3B0-3DE);
- and
- peripheral subsystem control circuitry (170) which asserts said peripheral subsystem memory address space read request signal (ADMR#) synchronously with said local bus clock signal (CLK) and nonsynchronously with said I/O bus clock signal (BCLK) and which enables said second data path (144, 146, 148, 150;
- 110), both in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF), said second data path (144, 146, 148, 150;
- 110) not being enabled in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF),
- said peripheral subsystem control circuitry (170) further enabling said second data path (144, 146, 148, 150;
- 110) in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3BO-3DE), said second data path (144, 146, 148, 150;
- 110) not being enabled in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3BO-3DE).
17 more elements
Computer apparatus for use with a local device (116) having address (CA, BE#), data (CD) and control (M/IO#, W/R#, ADS#) lines, and having a local bus clock signal carrying a local bus clock signal (CLK), said local device (116) being able to initiate a local device memory address space write access cycle to a first desired address in a memory address space by placing said first address on said address lines and issuing a first predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK), said local device (116) also being able to initiate a local device I/O address space write access cycle to a second desired address in an I/O address space distinct from said memory address space, by placing said second address on said address lines and issuing a second predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK),
- for use further with a peripheral subsystem (12) receiving control signals and having peripheral subsystem port leads (DB(15:0)) carrying data, said control signals received by said peripheral subsystem (12) including a peripheral subsystem memory address space write request signal (CDMW#) and a peripheral subsystem I/O address space write request signal (MIOW#), each of said peripheral subsystem write request signals (CDMW#, MIOW#) being received by said peripheral subsystem (12) in conjunction with a respective address received by said peripheral subsystem (12), said peripheral subsystem (12) writing data from said peripheral subsystem port leads (DB(15:0)) in response to said peripheral subsystem memory address space write request signal (CDMW#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem memory address space write request signal (CDMW#) is within a first predefined set of addresses (A0000-BFFFF) in said memory address space, and said peripheral subsystem (12) also writing data from said peripheral subsystem port leads (DB(15:0)) in response to said peripheral subsystem I/O address space write request signal (MIOW#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem I/O address space write request signal (MIOW#) is within a second predefined set of addresses (3B0-3DE) in said I/O address space,
- for use further with an I/O bus carrying data and control signals, said I/O bus carrying an I/O bus clock signal (BCLK) having a maximum frequency which is slower than that of said local bus clock signal (CLK), said I/O bus control signals including an I/O bus memory address space write request signal (MEMW#) which when asserted indicates a write access to an address in said memory address space, said I/O bus control signals further including an I/O bus I/O address space write request signal (IOW#) which when asserted indicates a write access to an address in said I/O address space,
- said apparatus comprising:
- a first data path (110;
- 114) which only when enabled couples any of said data on said data lines of said local device (116) to said I/O bus;
- a second data path (110;
- 144, 146, 148, 150) which only when enabled couples said data lines of said local device (116) to said peripheral subsystem port leads (DB(15:0));
- bus interface control circuitry (114) which asserts said I/O bus memory address space write request signal (MEMW#) synchronously with said I/O bus clock signal (BCLK) and enables said first data path (110;
- 114), both in response to a local device memory address space write access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF),
- said bus interface control circuitry (114) further asserting said I/O bus I/O address space write request signal (IOW#) synchronously with said I/O bus clock signal (BCLK) and enabling said first data path (110;
- 114), both in response to a local device I/O address space write access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3BO-3DE);
- and
- peripheral subsystem control circuitry (170) which asserts said peripheral subsystem memory address space write request signal (CDMW#) synchronously with said local bus clock signal (CLK) and nonsynchronously with said I/O bus clock signal (BCLK) and which enables said second data path (110;
- 144, 146, 148, 150), both in response to a local device memory address space write access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (AOOOO-BFFFF),
- said peripheral subsystem control circuitry (170) further enabling said second data path (110;
- 144, 146, 148, 150) in response to a local device I/O address space write access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3BO-3DE).
13 more elements
Computer apparatus comprising:
- a CPU subsystem (116, 110) having address leads (CA, BE#), data leads (CD) and control leads (M/IO#, ADS#);
- an I/O subsystem (112, 120, 122, 154, 124, 126) having address leads (SA, LA, XA) and data leads (SD, XD);
- a video controller (12) having address leads (A(19:16), DB(15:0)) and data leads (DB(15:0));
- interface coupling circuitry (in 114) coupled to communicate data only when enabled, between said CPU subsystem data leads (CD) and at least some of said I/O subsystem data leads (SD, XD);
- a data buffer (144, 146;
- 148, 150) connected directly between said CPU subsystem data leads (CD) and said video controller data leads (DB(15:0)), said data buffer communicating data between said CPU subsystem data leads (CD) and said video controller data leads (DB(15:0)) only when enabled;
- and
- control means for enabling said interface coupling circuitry (114) in response to a first predefined combination of signals (M/IO#=M;
- ADS#=Active) on said CPU subsystem control leads only when said CPU subsystem address leads (CA, BE#) carry an address which is within a first predefined set of addresses,
- and for enabling said data buffer (144, 146;
- 148, 150) in response to said first predefined combination of signals (M/IO#=M;
- ADS#=Active) on said CPU subsystem control leads only when said CPU subsystem address leads (CA, BE#) carry an address which is within a second predefined set of addresses distinct from said first predefined set of addresses.
- said apparatus lacking any buffers connected directly between any of said I/O subsystem data leads (SD, XD) and said video controller data leads (DB(15:0)).
10 more elements
Dependencies are inferred from the claim text.