US 5,309,567 AGranted

Structure and method for an asynchronous communication protocol between master and slave processors

AssigneeC-Cube Microsystems, Inc.

InventorToshiaki Mizukami

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Abstract

In accordance with the present invention, a structure and a method for asynchronously interfacing a master processor and a slave processor is provided by receiving from and providing to the master device control signals of a polling protocol, and receiving from and providing to the slave device control signals of an interrupt type protocol. In a first embodiment of this invention, the master processor provides WR (write request), RD (read request), OE (output enable) signals, and receives a BUSY (busy) signal. The slave processor receives an "int" (interrupt) signal, and provides "intack" (interrupt acknowledge), "outs" (output), and "ins" (input) signals. In a second embodiment of this invention, instead of the RD signal of the first embodiment, the read request signal is the AND product of an AS (address strobe) signal and the most significant bit of the read address.

Claims14

Dependent claims

A structure for interfacing a master processor to a slave processor comprising:

means for receiving a write request signal from said master processor;
means for receiving from said master processor data associated with said write request signal;
means coupled to said write request signal receiving means, for providing an interrupt signal to said slave processor in response to said write request signal;
means, coupled to said write request signal receiving means, for providing a slave processor busy signal to said master processor upon receiving said write request signal;
means for receiving an interrupt acknowledge signal from said slave processor;
means, coupled to said means for providing an interrupt signal and said means for receiving an interrupt acknowledge signal, for inactivating said interrupt signal upon receiving said interrupt acknowledge signal;
means for receiving from said slave processor an input strobe signal;
means, coupled to said means for receiving data and said means for receiving an input strobe signal, for transferring said data to said slave processor upon receiving said input strobe signal from said slave processor;
and
means, coupled to said means for transferring data and said means for providing a slave processor busy signal, for inactivating said slave processor busy signal after said transferring of data to said slave processor is complete.

7 more elements

Dependencies are inferred from the claim text.