Synchronous processor unit with interconnected, separately clocked processor sections which are automatically synchronized for data transfer operations

In a data processor of the type formed with a first data processing circuit group including a main bus means and a second data processing circuit group including an extended bus means, coupled together through said respective bus means for communicating information thereon, the first data processing circuit group including an instruction executing means for executing instructions to perform data processing operations, the instructions including data transfer instructions for transferring information between the first and second data processing circuit groups, apparatus for providing first and second clocks, each of a different frequency from the other, for synchronizing one transition of the first clock and with one transition of the second clock when a data transfer instruction is being executed by the instruction executing means, the apparatus comprising:

• clock generating means for providing the first and second clocks, the clock generating means including means coupled to receive an indicia of the instruction being executed by the instruction execution mean and responsive thereto to effect substantial coincidence between a predetermined transition of the first and second clock signals when the instruction execution means is executing a data transfer instruction;
• and
• detecting means coupled to the instruction execution means to receive the indicia of the instruction being executed to communicate the main and extended data buses to one another for a time period that includes the coincidence in transitions of the first and second clock signals when the instruction execution means is executing a data transfer instruction.

A data processor, comprising:

• a first processing section operating in response to a first clock signal and including first circuit means for performing at least arithmetic, logic, and data transfer operations in response to instructions, including data transfer instructions, memory means for storing data and the instructions, the first bus means inter-coupling the first circuit means and the memory means for communicating digital information therebetween when the first processing section is executing data transfer instructions;
• a second processing section operating in response to a second clock signal, the frequency of the second clock signal being different from that of the first clock signal, the second processing section including a second bus means;
• clock generating means operable in a one mode for generating first and second clock signals, and in a momentary mode in which at least one transition of the first clock signal and one transition of the second clock signal occur substantially at the same moment in time, the clock generating means including means coupled to detect data transfer instructions being executed by the first circuit means to operate the clock generating means in the momentary mode;
• and
• means coupling the first bus means to the second bus means and responsive to the first circuit means executing a data transfer instruction to communicate the first and second buses to one another for a period of time that includes the moment in time, and to prohibit communication between the first and second buses at all other times;