Space compression technique for pseudo-exhaustive self-testing of digital electronic circuits
AssigneeAT&T Bell Laboratories
InventorsMarsha R. Moskowitz, Eleanor Wu
Life of this patent
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Abstract
Compaction of the response signals produced by separate sets of sub-circuits (12.sub.i) within a digital circuit (10) under test is accomplished by first analyzing each response signal produced by a corresponding set of sub-circuits (by way of a logic analyzer (16,18)) to determine if the response signal has a particular pattern. A pattern bit is then set in accordance with the response signal which has the particular pattern. The pattern bits are then compacted by a set of daisy-chained time compactors (20), each compactor serving to exclusively OR the pattern bit from a corresponding logic analyzer (16,18) with a compacted bit generated previously by an upstream compactor.
Claims5
A method for compacting a plurality of response signals, each generated by a separate set of sub-circuits within an electronic digital circuit under test, comprising the steps of:
- logically analyzing each response signal generated by each set of sub-circuits and generating a pattern bit indicative of whether that response signal has a particular pattern;
- time compacting each pattern bit of each set of sub-circuits by exclusively OR'ing it with a compacted bit generated previously by the same subset of circuits to yield a current compacted bit for subsequent exclusive OR'ing with a subsequently generated pattern bit associated with a different set of sub-circuits;
- and
- repeating the steps of logically analyzing each response signal and time-compacting each pattern bit for a predetermined number of times.
Apparatus for compacting a plurality of streams of response signals, each response signal produced by a separate set of sub-circuits within an electronic digital circuit under test, comprising:
- a plurality of logic-analyzing means, each serving to analyze the response signal generated by a separate set of sub-circuits and producing a response bit indicative of whether the response signal produced by the corresponding sub-circuit has a particular pattern;
- and
- a plurality of time-compaction means, each associated with each logic-analyzing means and connected in a daisy-chain fashion in a loop for producing a time-compacted bit in accordance with both the pattern bit from the corresponding logic-analyzing means connected thereto and with a time-compacted bit produced previously by a time-compaction means associated with another logic analyzer means.
Dependencies are inferred from the claim text.