Test validation method for a semiconductor memory device
AssigneeTexas Instruments Incorporated
InventorsDanny R. Cline, Wah K. Loh, Adin E. Hyslop, Hugh P. McAdams, Chok Y. Hung
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Abstract
A test validation process for a semiconductor device applies signals indicating a test mode to the semiconductor device. The device produces output signals and the output signals are read to determine whether the device is in the indicated test mode. The test mode is conducted by operating the device. The output signals are read upon completion of the test mode to determine if the device is still in the indicated test mode. The test validation method is useful for memory chips and particularly Dynamic Random Access Memory, DRAM, devices that are burn-in stress tested.
Claims7
A process of validating a test of a semiconductor device where the device is capable of operating in plural internal test modes, the process comprising:
- A. applying to the device signals that indicate that the device should enter at least one of the internal test modes;
- B. producing from the device output signals that indicate the test mode entered by the device in response to the applied signals;
- C. reading the output signals to determine whether the device entered the indicated test mode;
- D. operating the device to conduct the indicated test;
- and
- E. reading the output signals to determine whether the device remained in the indicated test mode during the indicated test.
Dependencies are inferred from the claim text.