ATM cell delay circuit for ISDN system

Abstract

A circuit for applying delays to ATM cells in an ISDN comprises a dummy cell generating circuit for generating dummy cells at a controllable time interval, a first cell filter for extracting from an input signal only those cells to which delays are to be applied, a cell multiplexing circuit for synthesizing an output of the dummy cell generating circuit and an output of the cell filter, a delay adding circuit for delaying an output of the cell multiplexing circuit, and a second cell filter for eliminating the dummy cells from the output of the delay adding circuit. In case the dummy cell generating circuit is arranged to generate idle cells, the second cell filter is omitted. By multiplexing the signal cells inputted to the delay adding circuit with the dummy cells, the time taken for the input cells to pass through a shift register constituting the delay adding circuit can be controlled.

Dependencies are inferred from the claim text.