Sense circuit for non-volatile memory device

A sense circuit for a non-volatile memory device which includes a plurality of cell transistors which form memory cells, each cell transistor being connected to one of a plurality of word lines and to one of a plurality of bit lines, said bit lines being connected to a bus line, said sense circuit comprising:

• selecting means coupled to the bus line for selecting a predetermined cell transistor by selecting a predetermined bit line which is connected to the predetermined cell transistor;
• a feedback type bias circuit coupled to said selecting means for maintaining a potential of the bus line to a constant level, said feedback type bias circuit including a first transistor which flows a current to the bus line;
• detecting means coupled to said feedback type bias circuit for detecting whether or not a current flows through the predetermined cell transistor so as to read a data from the predetermined cell transistor, said detecting means including a terminal for outputting the read data;
• and
• current source means coupled to said feedback type bias circuit, said current source means including a second transistor for forcibly supplying a predetermined current to said first transistor, so that a gate-source voltage of said first transistor is greater than a threshold voltage of said first transistor and wherein said second transistor for supplying a bias current maintains the conductance of said first transistor in a linear conducting region of its conductance characteristic.