Input buffer circuit, input/output buffer circuit and portable semiconductor memory device with back-up power

An input buffer circuit for a semiconductor memory comprising:

• an input/output bus,
• at least one bidirectional buffer connected to said input/output bus,
• a first power supply line for supplying power to said bidirectional buffer from a first power supply,
• a power cutoff circuit connected in series between said bidirectional buffer and said first power supply line, said power cutoff circuit connecting said first power supply line to said bidirectional buffer when a voltage exceeding a predetermined threshold voltage is applied to said first power supply line by said first power supply and disconnecting said first power supply line from said bidirectional buffer when a voltage not exceeding the predetermined threshold voltage is applied to said first power supply line,
• an impedance lowering circuit connected to the at least one bidirectional buffer and said input/output bus for lowering impedance of said input/output bus when the voltage applied to said first and second power supply line does not exceed the predetermined threshold voltage, said impedance lowering circuit including "L" level output means for outputting a signal of "L" level to said input/output bus from said bidirectional buffer when the predetermined threshold voltage is not applied by said first power supply line.
• a second power supply line for supplying power from a second power supply to said impedance lowering circuit, and
• power control means disconnecting said first power supply line from said second power supply line when the voltage applied to said first power supply line is below the predetermined threshold voltage, said second power supply line being connected to said first power supply line when the voltage applied to said first power supply line exceeds the predetermined voltage threshold.

A portable semiconductor memory device comprising:

• a semiconductor memory including an input bus having an impedance and an input/output bus having an impedance,
• an internal power line connected to said semiconductor memory,
• an external power input line,
• a power control circuit for connecting said external power input line to said internal power line only when a voltage on said external power input line exceeds a predetermined threshold,
• an input buffer circuit having an internal buffer coupled to said input bus of said semiconductor memory and connected to said external power input line,
• an input/output buffer circuit having an internal buffer coupled to said input/output bus of said semiconductor memory and connected to the external power input line,
• power cutoff means for connecting said internal buffer of said input buffer circuit and said internal buffer of said input/output buffer circuit to said external power input line when the voltage on said external power input line exceeds the predetermined threshold and for disconnecting said internal buffer of said input buffer circuit and said internal buffer of said input/output buffer circuit from said external power input line when the voltage of said external power input line does not exceed the predetermined threshold, and
• impedance lowering means connected to said input bus and said input/output bus and including a first input impedance lowering circuit for lowering the impedance of said input bus of said semiconductor memory, said first impedance lowering circuit including a unidirectional buffer having an input connected to an output of said input buffer circuit and an output connected to said input bus of said semiconductor memory, and first "L" level output means for outputting a signal of "L" level to the input of said unidirectional buffer only when the voltage on said external power input line does not exceed the predetermined threshold, and a second impedance lowering circuit for lowering the impedance of said input/output bus of said semiconductor memory when the voltage on said external power input line does not exceed the predetermined threshold.