Back to results
US 5,309,393 AGranted
Semiconductor memory device
AssigneeHitachi, Ltd.
InventorsTakeshi Sakata, Katsutaka Kimura, Kiyoo Itoh
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device of the invention realizes a reduced memory array area decreasing the number of connection holes between data-lines and memory cells. The memory cell is made up of one transistor and one capacitor. The plurality of memory cells are connected in such a way that the transisters are connected in series to one another. The individual electrodes of the capacitors are connected to the respective connection of the transistors. By applying a voltage to the word-lines in order, the information stored as charge in respective capacitors is read out to the data-line.
Claims42
A semiconductor memory device including:
- a plurality of word lines;
- a plurality of switches each of which is controlled by a corresponding one of said plurality of word lines;
- and
- a plurality of information storage means each of which is coupled between a corresponding one of said plurality of switches and a reference potential,
- wherein a memory cell block includes a plurality of memory cells each of which comprises a corresponding one of said plurality of information storage means, a corresponding one of said plurality of switches and a corresponding one of said plurality of word lines, and
- wherein said plurality of switches of said plurality of memory cells are so connected in series that the information storage means of one of said plurality of memory cells is coupled between the switch of said one memory cell and the switch of the adjacent memory cell, wherein information of said information storage means of said one memory cell is read out on a signal terminal through said switch of said one memory cell and said switch of said adjacent memory cell, and wherein information is written into said information storage means of said one memory cell through said signal terminal, said switch of said adjacent memory cell and said switch of said one memory cell.
3 more elements
A semiconductor memory device including:
- a plurality of word-lines;
- a plurality of switches selected by said word-lines;
- and
- a plurality of information storage means being controlled of signal transfer by said switches,
- wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block;
- wherein said memory device includes a data-line, and a plurality of said memory cell blocks are connected to said data-lines;
- wherein sense means for sensing a signal read out from said memory cell block is provided and said sense means is connected to said data-lines, and
- wherein said semiconductor memory device includes a register circuit for temporarily storing therein information sensed by said sense means.
5 more elements
A semiconductor memory device including:
- a plurality of word-lines;
- a plurality of switches selected by said word-lines;
- and
- a plurality of information storage means being controlled of signal transfer by said switches,
- wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block;
- wherein said memory device includes a data-line, and a plurality of said memory cell blocks are connected to said data-lines;
- wherein sense means for sensing a signal read out from said memory cell block is provided and said sense means is connected to said data-lines;
- and
- wherein the reading and writing operation is performed in such a way that information read out from a certain memory cell block is sensed by said sense means, and the sensed result is written to other memory cell block connected to the same data-line as that of said certain memory cell block.
6 more elements
A semiconductor memory device including:
- a plurality of word-lines;
- a plurality of switches selected by said word-lines;
- and
- a plurality of information storage means being controlled of signal transfer by said switches,
- wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block;
- wherein said memory device includes a data-line, and a plurality of said memory cell blocks are connected to said data-lines;
- wherein said plurality of memory cell blocks are connected to the data-line through signal transfer means, and said signal transfer means transfers a signal in the reading operation in a state in which an input impedance from said memory cell blocks is high;
- including therein a plurality of said data-lines to each of which said plurality of memory cell blocks are connected;
- including therein a dummy data-line provided in common in said plurality of data-lines,
- a plurality of signal converting means connected to said plurality of data-lines and said dummy data-line, respectively, and a plurality of differential signal sense means provided corresponding to the signal converting means provided in said plurality of data-lines,
- wherein an output of the signal converting means provided in each of said data-lines, and an output of the signal converting means provided in said dummy data-line are inputted to each of said differential signal sense means.
8 more elements
A semiconductor memory device including:
- a plurality of word-lines;
- a plurality of switches selected by said word-lines, and
- a plurality of information storage means being controlled of signal transfer by said switches,
- wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block;
- wherein said memory device includes a data-line, and a plurality of said memory blocks are connected to said data-lines;
- wherein said plurality of memory cell blocks are connected to the data-line through signal transfer means, and said signal transfer means transfers a signal in the reading operation in a state in which an input impedance from said memory cell blocks is high;
- including therein a plurality of said data-lines to each of which said plurality of memory cell blocks are connected;
- wherein said signal converting means is provided in common in said plurality of data-lines and a plurality of dummy data-lines, and switch means is provided for connecting said signal converting means and each of said plurality of data-lines and said plurality of dummy data-lines to each other.
5 more elements
A semiconductor memory device including:
- a plurality of word-lines;
- a plurality of switches selected by said word-lines;
- and
- a plurality of information storage means being controlled of signal transfer by said switches,
- wherein a memory cell block is connected by connecting at least two memory cells each of which comprises a corresponding one of said plurality of information storage means, a corresponding one of said plurality of switches and a corresponding one of said plurality of word lines, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block;
- wherein said capacitor is made up of an electrode which is in contact with one impurity-doped region of said transistor and extends over said transistor and data-line, an insulating film provided on said electrode, and a conductive electrode provided on said insulating film.
3 more elements
Dependencies are inferred from the claim text.