Floating-point division circuit

A floating-point division circuit comprising:

• a circuit portion performing pre-division processing and pattern determination on floating point data, including a divisor and a dividend;
• an exponent operation portion performing operations on exponent parts of floating-point data, including said divisor and said dividend subject to pre-processing by said circuit portion;
• a control portion generating a non-executional signal that is active only when no instruction for division is performed;
• a mantissa division portion, into which mantissa parts of floating-point data, including said divisor and dividend subject to pre-processing by said circuit portion, are input, generating mantissa part data of a quotient by performing repeated procedures based on a predetermined algorithm;
• and
• a quotient generating circuit portion generating a quotient consisting of a predetermined number of bits on the basis of output data from said exponent operation portion and mantissa division portion, wherein
• said non-executional signal stops repeated operations of said mantissa division portion by stopping latch operations of a register in said mantissa division portion.

A floating-point division circuit comprising:

• a circuit portion performing pre-division processing and pattern determination on floating-point data, including a divisor and a dividend;
• an exponent operation portion performing operations on exponent parts of floating-point data, including said divisor and said dividend subject to pre-processing by said circuit portion;
• a control portion outputting a control signal on the basis of a count obtained by counting clocks while an instruction for division is executed, and maintaining said count fixed while an instruction for division is not executed by halting said count, invalidating said control signal;
• a mantissa division portion into which mantissa parts of the floating-point data, including said divisor and said dividend subject to pre-processing by said circuit portion, are input wherein procedures based on a predetermined algorithm are repeated to generate a mantissa part data of a quotient;
• and
• a quotient generating circuit portion generating a quotient consisting of a predetermined number of bits on the basis of output data from said exponent operation portion and mantissa division portion, wherein
• said control signal controls a latch operation of a register in said quotient generating circuit portion.

A floating-point division circuit comprising:

• a circuit portion performing pre-division processing and pattern determination on floating point data, including a divisor and a dividend;
• an exponent operation portion performing operations on exponent parts of floating-point data, including said divisor and said dividend subject to pre-processing by said circuit portion;
• an exception/non-operation detecting portion determining a predetermined non-operational pattern on the basis of a result of pattern determination obtained in said circuit portion with regard to said divisor and said dividend, and generating a stop signal when said non-operational pattern is detected;
• a mantissa division portion into which mantissa parts of floating-point data, including said divisor said dividend subject to pre-processing by said circuit portion, are input wherein procedures based on a predetermined algorithm are repeated to generate a mantissa part data of a quotient;
• and
• quotient generating portions generating a quotient consisting of a predetermined number of bits on the basis of output data from said exponent operation portion, exception/non-operation detecting portion, and mantissa division portion, wherein
• said non-executional signal and stop signal stops repeated operations of said mantissa division portion by stopping a latch operation of a register in said mantissa division portion.

A floating-point division circuit comprising:

• a circuit portion performing pre-division processing and pattern determination on floating-point data, including a divisor and a dividend;
• an exponent operation portion performing operations on exponent parts of floating-point data, including said divisor and said dividend subject to pre-processing by said circuit portion;
• a control portion which outputs a control signal;
• an exceptional/non-operation detecting portion determining a predetermined non-operational pattern on the basis of a result of pattern determination obtained in said circuit portion with regard to said divisor and said dividend, and generating a stop signal when said non-operational pattern is detected;
• a mantissa division portion into which mantissa parts of the floating-point data, including said divisor and said dividend subject to pre-processing by said circuit portion, are input wherein procedures based on a predetermined algorithm are repeated in order to generate a mantissa part data of a quotient;
• and
• a quotient generating circuit portion generating a quotient consisting of a predetermined number of bits on the basis of output data from said exponent operation portion, the exception/non-operation detecting portion, and the mantissa division portion, wherein
• said stop signal stops a latch operation of a register in said mantissa division portion, and said control signal controls a latch operation of a register in said quotient generating circuit portion.

A floating-point division circuit comprising:

• a circuit portion performing pre-division processing and pattern determination on floating point data, including a divisor and a dividend;
• an exponent operation portion for performing operations on exponent parts of floating-point data, including said divisor and said dividend subject to pre-processing by said circuit portion;
• a control portion which outputs a control signal on the basis of a count obtained by counting clocks while an instruction for division is executed, and maintains said count fixed while an instruction for division is not executed by halting said count, invalidating said control signal outputting the non-executional signal that is active only when an instruction for division is not executed;
• a mantissa division portion into which mantissa parts of the floating-point data, including said divisor and said dividend subject to pre-processing by said circuit portion, are input wherein procedures based on a predetermined algorithm are repeated in order to generate a mantissa part data of a quotient;
• and
• a quotient generating circuit portion generating a quotient consisting of a predetermined number of bits on the basis of output data from said exponent operation portion and mantissa division portion, wherein
• said stop signal stops a latch operation of a register in said mantissa division portion, and said control signal controls a latch operation of a register in said quotient generating circuit portion.

A floating-point division circuit comprising:

• a circuit portion performing pre-division processing and pattern determination on floating-point data, including a divisor and a dividend;
• an exponent operation portion performing operations on exponent parts of floating-point data, including said divisor and dividend subject to preprocessing by said circuit portion;
• a control portion outputting a control signal on the basis of a count obtained by counting clocks while an instruction for division is executed, and maintaining said count fixed while an instruction for division is not executed by halting said count, invalidating said control signal outputting the non-executional signal that is active only when an instruction for division is not executed;
• an exceptional/non-operation detecting portion determining a predetermined non-operational pattern on the basis of a result of pattern determination obtained in said circuit portion with regard to said divisor and said dividend, and generating a stop signal when said non-operational pattern is detected;
• a mantissa division portion into which mantissa parts of the floating-point data, including said divisor and said dividend subject to pre-processing by said circuit portion, are input, wherein procedures based on a predetermined algorithm are repeated in order to generate a mantissa part data of a quotient;
• and
• a quotient generating circuit portion generating a quotient consisting of a predetermined number of bits on the basis of output data from said exponent operation portion, the exception/non-operation detecting portion, and the mantissa division portion, wherein
• said stop signal and a non-executional signal stops, when they are active, a latch operation of a register in said mantissa division portion, and said control signal controls a latch operation of a register in said quotient generating circuit portion.