US 5,309,371 AGranted

Method of and apparatus for designing circuit block layout in integrated circuit

AssigneeKawasaki Steel Corporation

InventorsHiromi Shikata, Yoshito Muraishi, Shoichi Moriya, Naoyasu Seki

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Abstract

There are provided a method of and an apparatus for designing a circuit block layout in an integrated circuit wherein minimization of a total wiring length among the circuit blocks and compaction of the circuit blocks are automatically achieved upon automatically laying out the circuit blocks and determining wiring among those circuit blocks, by initially laying out the circuit blocks using a spring model of a mass point system where circuit blocks with no size are coupled through springs, configuring at least partial circuit blocks as circles to re-lay out the circuit blocks such that there is eliminated any overlapping among the circuit blocks, compacting the external shape of an assembly of the circuit blocks by matching the external shape with the frame of a die and altering the shape of each circuit block from the circle to an actual shape.

Claims17

Dependent claims

A method of generating, in an automatic electronic design apparatus, electronic final layout data corresponding to a circuit block layout for manufacturing an integrated circuit, the automatic electronic design apparatus including a layout specification memory containing electronic circuit block data corresponding to circuit blocks, a layout information memory and a processing unit, said method comprising the steps of:

(a) from the electronic circuit block data, producing electronic rough layout data corresponding to an initial layout of said circuit blocks using a spring model of a mass point system in which infinitesimal circuit blocks are coupled through springs;
(b) from the electronic rough layout data, producing electronic revised layout data corresponding to a revised layout of said circuit blocks by representing at least some of said circuit blocks as circles and eliminating overlap among the circles;
(c) from said electronic revised layout data, generating electronic compacted layout data corresponding to a compacted layout of said circuit blocks to match an external perimeter shape of said circuit blocks as a whole with a frame of a die of the integrated circuit;
(d) altering the electronic compacted layout data to form electronic reshaped layout data corresponding to a layout of reshaped circuit blocks where the representation of the at least some of said circuit blocks is reshaped from a circle to an actual shape;
(e) from the electronic reshaped layout data, generating electronic expanded layout data corresponding to an expanded layout of circuit blocks by expanding each circuit block to provide a region for wiring;
(f) from the electronic expanded layout data, producing electronic fixed layout data by fixing positions of said circuit blocks after adjusting an aspect ratio of each circuit block within a corresponding allowable range;
and
(g) from electronic fixed layout data, producing the electronic final layout data by wiring within and between fixed circuit blocks.

5 more elements

An automatic electronic design apparatus having a layout specification memory containing electronic circuit block data corresponding to circuit blocks for generating electronic final layout data corresponding to a circuit block layout for manufacturing an integrated circuit comprising:

(a) means for producing, from the electronic circuit block data, electronic rough layout data corresponding to an initial layout of said circuit blocks using a spring model of a mass point system having an attractive force corresponding to a number of wire connections between said circuit blocks;
(b) means for producing, from the electronic rough layout data, electronic revised layout data corresponding to a revised layout of said circuit blocks using a spring model having a repulsive force corresponding to a degree of overlapping between said circuit blocks such that any overlapping among said circuit blocks according to said initial layout is eliminated;
and
(c) means for fixing, from the electronic revised layout data, electronic fixed layout data by fixing positions of said circuit blocks after adjusting a layout of said circuit blocks corresponding to a compacted layout of said circuit blocks such that said circuit blocks are laid out regularly in a matrix form;
and
(d) means for generating, from the electronic fixed layout data, the electronic final layout data by wiring between fixed circuit blocks.

3 more elements

Dependencies are inferred from the claim text.