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US 5,309,173 AGranted
Frame buffer, systems and methods
AssigneeTexas Instruments Incorporated
InventorsLouis J. Izzi, Richard E. Downing
Life of this patent
Estimating the term…
Abstract
A frame buffer is provided, including a plurality of input nodes and a plurality of multiplexing circuits. Each multiplexing circuit has a first input coupled to a respective input node. First control circuitry is provided for selectively coupling a second input of each multiplexer circuit to outputs of others of the multiplexing circuits. Second control circuitry is coupled to each multiplexing circuit for selecting between the first and second inputs.
Claims16
A buffer, comprising:
- k input nodes;
- a sequentially ordered array of k, multiplexing circuits, each multiplexing circuit having a first input coupled to a respective input node;
- a sequentially ordered array of j transmission gates associated with each multiplexing circuit;
- first control circuitry for selectively coupling a second input of an (n-2.sup.m-1)th one of said multiplexing circuits with an output of an n.sup.th one of said multiplexing circuits, wherein an mth one of said transmission gates is associated with an (n-2.sup.m-1)th one of said multiplexing circuits, j, k, m, and n being positive integers, j and k being constants, n being a variable that is greater than 2.sup.m-1, and m being a variable between 1 and j;
- second control circuitry coupled to each said multiplexing circuit for selecting between said first and second inputs;
- and
- a plurality of outputs coupled to said multiplexing circuits.
4 more elements
A frame buffer comprising:
- a sequentially ordered array of k multiplexers, each said multiplexer having first and second data inputs and a data output for passing data appearing at said first data inputs to said data outputs in response to a first control signal and for passing data appearing at said second data inputs to said outputs in response to a second control signal;
- a sequentially ordered array of k latches, each said latch having an input coupled to said data output of a respective said multiplexer and a latch output, for latching data appearing at said data outputs of said multiplexer;
- and
- a sequentially ordered array of j transmission gates, an mth one of said transmission gates associated with an (n-2.sup.m-1)th one of said multiplexers and operable to couple said second data input of an (n-2.sup.m-1)th one of said multiplexers with said latch output of an n.sup.th one of said latches, wherein j, k, m and n are positive integers, j and k being constants, n being a variable that is greater than 2.sup.m-1, and m being a variable between 1 and j.
1 more element
A color palette comprising:
- a first memory having a plurality of locations for containing a plurality of color codes;
- a second memory having a plurality of locations containing a plurality of color data words;
- a frame buffer operable to receive a selected one of said color codes from said first memory and output an address to said second memory in response, said address identifying a selected said location in said second memory containing a said selected color data word, said frame buffer comprising:
- a sequentially ordered array of r multiplexers each having first and second data inputs and a data output and operable to pass data appearing at said first data input in response to a control signal and operable to pass data appearing at said second data input in response to a first one of a sequence of clocking signals occurring after said control signal;
- a sequentially ordered array of r multiplexers, each said latch having an input coupled to said output of a respective said multiplexer and a latch output, said plurality of latches operable to latch data appearing at said outputs of said multiplexers to said latch outputs in response to said sequence of clocking signals;
- and
- a sequentially ordered array of j transmission gates, an mth one of said transmission gates associated with an (n-2.sup.m-1)th one of said multiplexers and operable to couple said second data input of an (n-2.sup.m-1)th one of said multiplexers with said latch output of an n.sup.th one of said latches, where j, r, m and n are positive integers, j and r being constants, m being a variable between 1 and j, and n being a variable that is greater than 2.sup.m-1.
4 more elements
Dependencies are inferred from the claim text.