Switched-capacitor circuit power down technique
AssigneeMotorola, Inc.
InventorsKing F. Lee, Norman T. Rollins
Life of this patent
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Abstract
A method and apparatus for reducing the settling time of a switched-capacitor circuit (10) which includes at least one capacitor (20) having at least one terminal connected to a switch. The method comprises the step of clocking the switched-capacitor circuit at a switching clocking frequency. In response to a control signal (51), the at least one terminal of the at least one capacitor (20) is biased to a reference voltage potential.
Claims16
A method for reducing settling time of a switched-capacitor circuit having at least one capacitor and one switch, said at least one capacitor having at least one terminal connected to said switch, the method comprising the steps of:
- clocking said switched-capacitor circuit with non-overlapping switching signals;
- and
- biasing said at least one terminal of said capacitor to a reference voltage potential, in response to a control signal and said non-overlapping switching signals.
A control network for reducing settling time of a switched-capacitor circuit including at least one capacitor having at least one terminal, and a switch, wherein said at least one terminal is connected to said switch, the control network comprising:
- means for clocking said switched-capacitor circuit at a switching clocking frequency wherein said means for clocking comprises a multi-phased clock generator for generating non-overlapping switching signals;
- and
- means for biasing said at least one terminal of said at least one capacitor to a reference voltage potential, in response to a control signal, wherein said means for biasing comprises means for ORing each of said non-overlapping switching signals with said control signal.
A switched-capacitor circuit and control arrangement comprising:
- a switched-capacitor circuit having switches connected to switchable internal circuit nodes;
- the switched-capacitor circuit including a plurality of non-overlapping multi-phase switching signals input terminals, an input node, and an output node;
- a control network for clocking said switched-capacitor circuit at a switching clocking frequency, in response to a normal status of a control signal, or for closing said switches for biasing the switchable internal circuit nodes of said switched-capacitor circuit to said analog ground voltage potential, in response to a power down mode status of said control signal;
- and
- the control network comprising:
- a transmission gate for connecting an input signal into said input node of said switched-capacitor circuit, in response to said normal mode status of said control signal;
- and
- means for ORing a plurality of non-overlapping multi-phase switching signals with said control signal to provide said non-overlapping multi-phase switching signal into said terminals, in response to said normal mode status of said control signal, or to provide a plurality of logic level high signals into said terminals, in response to said power down mode of said control signal.
Dependencies are inferred from the claim text.