Digital three-phase PWM signal

A digital three phase PWM signal generator comprising:

• a clock signal generating circuit for generating a clock signal of pulse having a predetermined period,
• an UP/DOWN counter for counting up said clock signal up to a predetermined number of pulses and for counting down from said predetermined number of pulses counted in the counting up operation, and for outputting counted value data during counting up operation and counting down operation,
• a first digital comparator for outputting a coincidence signal in coincidence of said counted value data in said UP/DOWN counter with zero,
• a first register for storing a peak value data representing the maximum counted value data in said UP/DOWN counter,
• a second digital comparator for comparing said counted value data in said UP/DOWN counter with said peak value data in said first register, and for outputting a coincidence signal in coincidence of said counted value data and said peak value data,
• a counting function switching circuit for switching said UP/DOWN counter to said counting up operation by receipt of said coincidence signal form said first digital comparator and for switching to said counting down operation by receipt of said coincidence signal from said second digital comparator,
• a second register for storing a threshold value data for generating a PWM signal for a first phase of a three-phase motor,
• a third register for storing a threshold value data for generating a PWM signal for a second phase of said three-phase motor,
• a fourth register for storing a threshold value data for generating a PWM signal for a third phase of said three-phase motor,
• a fifth register for storing the data in said second register by receipt of at least one of said coincidence signal from said first digital comparator and said coincidence signal from said second digital comparator,
• a sixth register for storing the data in said third register by receipt of at least one of said coincidence signal from said first digital comparator and said coincidence signal from said second digital comparator,
• a seventh register for storing the data in said fourth register by receipt of at least one of said coincidence signal from said first digital comparator and said coincidence signal from said second digital comparator,
• a third digital comparator for comparing the data of said fifth register with the data of said UP/DOWN counter, and for generating an output signal when the data of said fifth register is larger than the data of said UP/DOWN counter,
• a fourth digital comparator for comparing the data of said sixth register with the data of said UP/DOWN counter, and for generating an output signal when said data of said sixth register is larger than the data of said UP/DOWN counter, and
• a fifth digital comparator for comparing the data of said seventh register with the data of said UP/DOWN counter, and for generating and output signal when said data of said seventh register is larger than said data of said UP/DOWN counter.