Method and apparatus for clock skew reduction through absolute delay regulation
AssigneeDigital Equipment Corporation
InventorsRichard B. Watson, Jr., Hansel A. Collins, Russell Iknaian
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Abstract
An "absolute" delay regulator of a clock repeater chip performs a precise measurement of the propagation delay of a clock signal and adjusts that delay so as to maintain a fixed-phase relationship with an input clock signal. A replica loop accurately replicates the internal path and external loading, including input and output buffers, of the chip. The output of the replica loop drives a delay line whose tapped outputs provide an absolute delay measurement. Results of the measurement are decoded and used to select an appropriate tap to another delay line used to insert a desired amount of delay to an output clock signal.
Claims26
In a clock repeater chip having signal processing circuit components configured to receive periodic input clock signals and distribute processed output clock signals, a delay regulator for maintaining a fixed-phase relationship between said processed output clock signals and said input clock signals, said delay regulator comprising:
- means for generating a measurement pulse signal in response to one of said input signals, said measurement pulse signal having a leading edge and a trailing edge, and having a duration of an integral number of periods of said input signals;
- means for replicating a propagation delay of said input clock signals through said signal processing circuit components by using logic circuits configured to simulate the propagation delays of said signal processing components, said generating means being connected to apply said measurement pulse signal to an input end of said replicating means;
- means, connected to an output end of said replicating means, for measuring said replicated propagation delay in response to said trailing edge of said measurement pulse signal;
- and
- means responding to said measured propagation delay for adding a controlled amount of signal delay to the processed output clock signals provided by said signal processing circuitry, to allow said processed output clock signals to maintain said fixed-phase relationship with said input clock signals.
Apparatus for reducing clock skew in a synchronous computer system including a plurality of modules configured to operate in response to received system clock signals, said apparatus comprising:
- first means for generating said system clock signals;
- means, coupled to said first generating means, for distributing said system clock signals to the modules with a substantially constant phase, each of the modules having an integrated clock repeater circuit including signal processing circuitry configured to receive said system clock signals from said distributing means and supply output clock signals to an external load, said signal processing circuitry including a variable delay element, each clock repeater circuit further comprising:
- second means for generating a measurement pulse signal in response to one of said received system clock signals, said measurement pulse signal having a leading edge and a trailing edge;
- means for replicating a propagation delay of said received clock signals through the components of said signal processing circuitry except for said variable delay element, said replicating means including logic segments configured to simulate substantially all of the components of said signal processing circuitry, said second generating means being connected to apply said measurement pulse signal to an input end of said replicating means;
- means, coupled to an output end of said replicating means, for measuring said replicated propagation delay in response to said trailing edge of said measurement pulse signal;
- and
- means for translating said measured replicated propagation delay to a controlled delay interval in response to the results of said measuring means such that said variable delay element responds to said translating means to provide said controlled delay interval to said system clock signals processed by said signal processing circuitry and distributed to said load and said constant phase relationship is maintained among said output clock signals on the modules.
Dependencies are inferred from the claim text.