Integrated circuit package having stress reducing recesses
AssigneeNippon Precision Circuits Inc.
InventorKazuhiro Matsumoto
Life of this patent
Estimating the term…
Abstract
An integrated circuit device has reduced stress concentration on the IC chip for prevention of package cracks in the device. Recessed portions are formed in the package at positions corresponding to at least the corner portions of the IC chip to reduce the stress concentration generated at the corner portions of the IC chip.
Claims1
An integrated circuit device wherein an IC chip is molded in a resin package and extends in a given plane in said resin package, the resin package being formed of a resin having a coefficient of contraction that is different than that of the IC chip, the IC chip having corners, the resin package having an external surface extending parallel to said plane, at least one recess in said external surface, the bottom of said recess being positioned between said given plane and said external surface of said package, said recess being positioned to reduce stress concentration at said corners of said IC chip resulting from said different coefficients of contraction, said recess having a depth of from 0.1 mm to 0.2 mm and a width of from 0.1 mm to 2.0 mm.
Dependencies are inferred from the claim text.